| /hal_nxp-latest/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 471 base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | in SEMC_ConfigureSDRAM()
477 base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | in SEMC_ConfigureSDRAM()
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 309 MEM_WriteU32(0x400d4040, 0x00000F32); // SDRAMCR0, 32bit
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 309 MEM_WriteU32(0x400d4040, 0x00000F32); // SDRAMCR0, 32bit
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 33221 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 33242 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 34805 __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 36022 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 39071 __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 39432 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 36906 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 41107 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 41100 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm4.h | 64950 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| D | MIMXRT1175_cm7.h | 64048 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm7.h | 63546 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
|
| D | MIMXRT1165_cm4.h | 64448 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 64048 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm4.h | 69911 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| D | MIMXRT1166_cm7.h | 69009 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm4.h | 70410 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| D | MIMXRT1173_cm7.h | 69508 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 69511 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 80178 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| D | MIMXRT1176_cm4.h | 81080 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/ |
| D | MIMXRT1187_cm33.h | 73936 __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ member
|
