Searched refs:SDIO1FCLKDIV_OFFSET (Results 1 – 8 of 8) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_clock.h | 472 #define SDIO1FCLKDIV_OFFSET 0x694 macro
781 …kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_clock.h | 472 #define SDIO1FCLKDIV_OFFSET 0x694 macro
781 …kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_clock.h | 594 #define SDIO1FCLKDIV_OFFSET 0x694 macro
974 …kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_clock.h | 594 #define SDIO1FCLKDIV_OFFSET 0x694 macro
974 …kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_clock.h | 594 #define SDIO1FCLKDIV_OFFSET 0x694 macro
974 …kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/ |
| D | fsl_clock.h | 939 #define SDIO1FCLKDIV_OFFSET 0x284 macro
1749 …kCLOCK_DivSdio1Clk = CLKCTL4_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< SDIO1 Clk Divider…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/ |
| D | fsl_clock.h | 939 #define SDIO1FCLKDIV_OFFSET 0x284 macro
1749 …kCLOCK_DivSdio1Clk = CLKCTL4_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< SDIO1 Clk Divider…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/ |
| D | fsl_clock.h | 939 #define SDIO1FCLKDIV_OFFSET 0x284 macro
1749 …kCLOCK_DivSdio1Clk = CLKCTL4_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< SDIO1 Clk Divider…
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