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Searched refs:SDIF_STATUS_RESPONSE_INDEX_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h10640 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
10644 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h10455 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
10459 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h9663 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
9667 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h9996 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
10000 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h14144 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14148 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h13139 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
13142 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h14219 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14223 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h14556 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14560 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h14862 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14866 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h14864 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14868 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h15348 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
15352 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h14556 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14560 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h13845 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
13848 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h14787 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
14791 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h15348 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
15352 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h17928 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
17932 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h17927 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
17931 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h19584 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
19588 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h19583 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
19587 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h20182 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
20186 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
DLPC55S66_cm33_core0.h20182 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
20186 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h20181 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
20185 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
DLPC55S69_cm33_core0.h20181 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) macro
20185 …(uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)