1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SDA_AP.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SDA_AP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SDA_AP_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SDA_AP_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SDA_AP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SDA_AP_Peripheral_Access_Layer SDA_AP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SDA_AP - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t AUTHSTTS; /**< Authentication status register, offset: 0x0 */ 74 __O uint32_t AUTHCTL; /**< Authentication Control Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __I uint32_t KEYCHAL0; /**< Key Challenge 0 register, offset: 0x10 */ 77 __I uint32_t KEYCHAL1; /**< Key Challenge 1 register, offset: 0x14 */ 78 __I uint32_t KEYCHAL2; /**< Key Challenge 2 register, offset: 0x18 */ 79 __I uint32_t KEYCHAL3; /**< Key Challenge 3 register, offset: 0x1C */ 80 __I uint32_t KEYCHAL4; /**< Key Challenge 4 register, offset: 0x20 */ 81 __I uint32_t KEYCHAL5; /**< Key Challenge 5 register, offset: 0x24 */ 82 __I uint32_t KEYCHAL6; /**< Key Challenge 6 register, offset: 0x28 */ 83 __I uint32_t KEYCHAL7; /**< Key Challenge 7 register, offset: 0x2C */ 84 __IO uint32_t KEYRESP0; /**< Key Response 0 register, offset: 0x30 */ 85 __IO uint32_t KEYRESP1; /**< Key Response 1 register, offset: 0x34 */ 86 __IO uint32_t KEYRESP2; /**< Key Response 2 register, offset: 0x38 */ 87 __IO uint32_t KEYRESP3; /**< Key Response 3 register, offset: 0x3C */ 88 __IO uint32_t KEYRESP4; /**< Key Response 4 register, offset: 0x40 */ 89 __IO uint32_t KEYRESP5; /**< Key Response 5 register, offset: 0x44 */ 90 __IO uint32_t KEYRESP6; /**< Key Response 6 register, offset: 0x48 */ 91 __IO uint32_t KEYRESP7; /**< Key Response 7 register, offset: 0x4C */ 92 uint8_t RESERVED_1[32]; 93 __I uint32_t SDAUIDL; /**< UID Low Register, offset: 0x70 */ 94 __I uint32_t SDAUIDH; /**< UID High Register, offset: 0x74 */ 95 uint8_t RESERVED_2[8]; 96 __I uint32_t SDASYSRSTS; /**< System reset status register, offset: 0x80 */ 97 uint8_t RESERVED_3[4]; 98 __IO uint32_t SDASYSRSTC; /**< System Reset Control Register, offset: 0x88 */ 99 uint8_t RESERVED_4[4]; 100 __IO uint32_t SDARSTCTRL; /**< Reset Control Register, offset: 0x90 */ 101 __IO uint32_t SDARSTMASK; /**< Reset Control Mask Register, offset: 0x94 */ 102 uint8_t RESERVED_5[3428]; 103 __I uint32_t IDR; /**< Identification Register, offset: 0xDFC */ 104 uint8_t RESERVED_6[444]; 105 __I uint32_t DEVARCH; /**< CoreSight Device Architecture Register, offset: 0xFBC */ 106 uint8_t RESERVED_7[12]; 107 __I uint32_t DEVTYPE; /**< CoreSight Device Type Identifier Register, offset: 0xFCC */ 108 __I uint32_t PIDR4; /**< CoreSight Peripheral Identification Register 4, offset: 0xFD0 */ 109 uint8_t RESERVED_8[12]; 110 __I uint32_t PIDR0; /**< CoreSight Peripheral Identification Register 0, offset: 0xFE0 */ 111 __I uint32_t PIDR1; /**< CoreSight Peripheral Identification Register 1, offset: 0xFE4 */ 112 __I uint32_t PIDR2; /**< CoreSight Peripheral Identification Register 2, offset: 0xFE8 */ 113 __I uint32_t PIDR3; /**< CoreSight Peripheral Identification Register 3, offset: 0xFEC */ 114 __I uint32_t CIDR0; /**< CoreSight Component Identification Register 0, offset: 0xFF0 */ 115 __I uint32_t CIDR1; /**< CoreSight Component Identification Register 1, offset: 0xFF4 */ 116 __I uint32_t CIDR2; /**< CoreSight Component Identification Register 2, offset: 0xFF8 */ 117 __I uint32_t CIDR3; /**< CoreSight Component Identification Register 3, offset: 0xFFC */ 118 } SDA_AP_Type, *SDA_AP_MemMapPtr; 119 120 /** Number of instances of the SDA_AP module. */ 121 #define SDA_AP_INSTANCE_COUNT (1u) 122 123 /* SDA_AP - Peripheral instance base addresses */ 124 /** Peripheral SDA_AP base address */ 125 #define IP_SDA_AP_BASE (0x4DC71000u) 126 /** Peripheral SDA_AP base pointer */ 127 #define IP_SDA_AP ((SDA_AP_Type *)IP_SDA_AP_BASE) 128 /** Array initializer of SDA_AP peripheral base addresses */ 129 #define IP_SDA_AP_BASE_ADDRS { IP_SDA_AP_BASE } 130 /** Array initializer of SDA_AP peripheral base pointers */ 131 #define IP_SDA_AP_BASE_PTRS { IP_SDA_AP } 132 133 /* ---------------------------------------------------------------------------- 134 -- SDA_AP Register Masks 135 ---------------------------------------------------------------------------- */ 136 137 /*! 138 * @addtogroup SDA_AP_Register_Masks SDA_AP Register Masks 139 * @{ 140 */ 141 142 /*! @name AUTHSTTS - Authentication status register */ 143 /*! @{ */ 144 145 #define SDA_AP_AUTHSTTS_CHALRDY_MASK (0x1U) 146 #define SDA_AP_AUTHSTTS_CHALRDY_SHIFT (0U) 147 #define SDA_AP_AUTHSTTS_CHALRDY_WIDTH (1U) 148 #define SDA_AP_AUTHSTTS_CHALRDY(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_AUTHSTTS_CHALRDY_SHIFT)) & SDA_AP_AUTHSTTS_CHALRDY_MASK) 149 150 #define SDA_AP_AUTHSTTS_UIDRDY_MASK (0x4U) 151 #define SDA_AP_AUTHSTTS_UIDRDY_SHIFT (2U) 152 #define SDA_AP_AUTHSTTS_UIDRDY_WIDTH (1U) 153 #define SDA_AP_AUTHSTTS_UIDRDY(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_AUTHSTTS_UIDRDY_SHIFT)) & SDA_AP_AUTHSTTS_UIDRDY_MASK) 154 155 #define SDA_AP_AUTHSTTS_APPDBGEN_MASK (0x40000000U) 156 #define SDA_AP_AUTHSTTS_APPDBGEN_SHIFT (30U) 157 #define SDA_AP_AUTHSTTS_APPDBGEN_WIDTH (1U) 158 #define SDA_AP_AUTHSTTS_APPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_AUTHSTTS_APPDBGEN_SHIFT)) & SDA_AP_AUTHSTTS_APPDBGEN_MASK) 159 /*! @} */ 160 161 /*! @name AUTHCTL - Authentication Control Register */ 162 /*! @{ */ 163 164 #define SDA_AP_AUTHCTL_HSEAUTHREQ_MASK (0x1U) 165 #define SDA_AP_AUTHCTL_HSEAUTHREQ_SHIFT (0U) 166 #define SDA_AP_AUTHCTL_HSEAUTHREQ_WIDTH (1U) 167 #define SDA_AP_AUTHCTL_HSEAUTHREQ(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_AUTHCTL_HSEAUTHREQ_SHIFT)) & SDA_AP_AUTHCTL_HSEAUTHREQ_MASK) 168 /*! @} */ 169 170 /*! @name KEYCHAL0 - Key Challenge 0 register */ 171 /*! @{ */ 172 173 #define SDA_AP_KEYCHAL0_KEYCAL0_MASK (0xFFFFFFFFU) 174 #define SDA_AP_KEYCHAL0_KEYCAL0_SHIFT (0U) 175 #define SDA_AP_KEYCHAL0_KEYCAL0_WIDTH (32U) 176 #define SDA_AP_KEYCHAL0_KEYCAL0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL0_KEYCAL0_SHIFT)) & SDA_AP_KEYCHAL0_KEYCAL0_MASK) 177 /*! @} */ 178 179 /*! @name KEYCHAL1 - Key Challenge 1 register */ 180 /*! @{ */ 181 182 #define SDA_AP_KEYCHAL1_KEYCAL1_MASK (0xFFFFFFFFU) 183 #define SDA_AP_KEYCHAL1_KEYCAL1_SHIFT (0U) 184 #define SDA_AP_KEYCHAL1_KEYCAL1_WIDTH (32U) 185 #define SDA_AP_KEYCHAL1_KEYCAL1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL1_KEYCAL1_SHIFT)) & SDA_AP_KEYCHAL1_KEYCAL1_MASK) 186 /*! @} */ 187 188 /*! @name KEYCHAL2 - Key Challenge 2 register */ 189 /*! @{ */ 190 191 #define SDA_AP_KEYCHAL2_KEYCAL2_MASK (0xFFFFFFFFU) 192 #define SDA_AP_KEYCHAL2_KEYCAL2_SHIFT (0U) 193 #define SDA_AP_KEYCHAL2_KEYCAL2_WIDTH (32U) 194 #define SDA_AP_KEYCHAL2_KEYCAL2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL2_KEYCAL2_SHIFT)) & SDA_AP_KEYCHAL2_KEYCAL2_MASK) 195 /*! @} */ 196 197 /*! @name KEYCHAL3 - Key Challenge 3 register */ 198 /*! @{ */ 199 200 #define SDA_AP_KEYCHAL3_KEYCAL3_MASK (0xFFFFFFFFU) 201 #define SDA_AP_KEYCHAL3_KEYCAL3_SHIFT (0U) 202 #define SDA_AP_KEYCHAL3_KEYCAL3_WIDTH (32U) 203 #define SDA_AP_KEYCHAL3_KEYCAL3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL3_KEYCAL3_SHIFT)) & SDA_AP_KEYCHAL3_KEYCAL3_MASK) 204 /*! @} */ 205 206 /*! @name KEYCHAL4 - Key Challenge 4 register */ 207 /*! @{ */ 208 209 #define SDA_AP_KEYCHAL4_KEYCAL4_MASK (0xFFFFFFFFU) 210 #define SDA_AP_KEYCHAL4_KEYCAL4_SHIFT (0U) 211 #define SDA_AP_KEYCHAL4_KEYCAL4_WIDTH (32U) 212 #define SDA_AP_KEYCHAL4_KEYCAL4(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL4_KEYCAL4_SHIFT)) & SDA_AP_KEYCHAL4_KEYCAL4_MASK) 213 /*! @} */ 214 215 /*! @name KEYCHAL5 - Key Challenge 5 register */ 216 /*! @{ */ 217 218 #define SDA_AP_KEYCHAL5_KEYCAL5_MASK (0xFFFFFFFFU) 219 #define SDA_AP_KEYCHAL5_KEYCAL5_SHIFT (0U) 220 #define SDA_AP_KEYCHAL5_KEYCAL5_WIDTH (32U) 221 #define SDA_AP_KEYCHAL5_KEYCAL5(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL5_KEYCAL5_SHIFT)) & SDA_AP_KEYCHAL5_KEYCAL5_MASK) 222 /*! @} */ 223 224 /*! @name KEYCHAL6 - Key Challenge 6 register */ 225 /*! @{ */ 226 227 #define SDA_AP_KEYCHAL6_KEYCAL6_MASK (0xFFFFFFFFU) 228 #define SDA_AP_KEYCHAL6_KEYCAL6_SHIFT (0U) 229 #define SDA_AP_KEYCHAL6_KEYCAL6_WIDTH (32U) 230 #define SDA_AP_KEYCHAL6_KEYCAL6(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL6_KEYCAL6_SHIFT)) & SDA_AP_KEYCHAL6_KEYCAL6_MASK) 231 /*! @} */ 232 233 /*! @name KEYCHAL7 - Key Challenge 7 register */ 234 /*! @{ */ 235 236 #define SDA_AP_KEYCHAL7_KEYCAL7_MASK (0xFFFFFFFFU) 237 #define SDA_AP_KEYCHAL7_KEYCAL7_SHIFT (0U) 238 #define SDA_AP_KEYCHAL7_KEYCAL7_WIDTH (32U) 239 #define SDA_AP_KEYCHAL7_KEYCAL7(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYCHAL7_KEYCAL7_SHIFT)) & SDA_AP_KEYCHAL7_KEYCAL7_MASK) 240 /*! @} */ 241 242 /*! @name KEYRESP0 - Key Response 0 register */ 243 /*! @{ */ 244 245 #define SDA_AP_KEYRESP0_KEYCAL0_MASK (0xFFFFFFFFU) 246 #define SDA_AP_KEYRESP0_KEYCAL0_SHIFT (0U) 247 #define SDA_AP_KEYRESP0_KEYCAL0_WIDTH (32U) 248 #define SDA_AP_KEYRESP0_KEYCAL0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP0_KEYCAL0_SHIFT)) & SDA_AP_KEYRESP0_KEYCAL0_MASK) 249 /*! @} */ 250 251 /*! @name KEYRESP1 - Key Response 1 register */ 252 /*! @{ */ 253 254 #define SDA_AP_KEYRESP1_KEYCAL1_MASK (0xFFFFFFFFU) 255 #define SDA_AP_KEYRESP1_KEYCAL1_SHIFT (0U) 256 #define SDA_AP_KEYRESP1_KEYCAL1_WIDTH (32U) 257 #define SDA_AP_KEYRESP1_KEYCAL1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP1_KEYCAL1_SHIFT)) & SDA_AP_KEYRESP1_KEYCAL1_MASK) 258 /*! @} */ 259 260 /*! @name KEYRESP2 - Key Response 2 register */ 261 /*! @{ */ 262 263 #define SDA_AP_KEYRESP2_KEYCAL2_MASK (0xFFFFFFFFU) 264 #define SDA_AP_KEYRESP2_KEYCAL2_SHIFT (0U) 265 #define SDA_AP_KEYRESP2_KEYCAL2_WIDTH (32U) 266 #define SDA_AP_KEYRESP2_KEYCAL2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP2_KEYCAL2_SHIFT)) & SDA_AP_KEYRESP2_KEYCAL2_MASK) 267 /*! @} */ 268 269 /*! @name KEYRESP3 - Key Response 3 register */ 270 /*! @{ */ 271 272 #define SDA_AP_KEYRESP3_KEYCAL3_MASK (0xFFFFFFFFU) 273 #define SDA_AP_KEYRESP3_KEYCAL3_SHIFT (0U) 274 #define SDA_AP_KEYRESP3_KEYCAL3_WIDTH (32U) 275 #define SDA_AP_KEYRESP3_KEYCAL3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP3_KEYCAL3_SHIFT)) & SDA_AP_KEYRESP3_KEYCAL3_MASK) 276 /*! @} */ 277 278 /*! @name KEYRESP4 - Key Response 4 register */ 279 /*! @{ */ 280 281 #define SDA_AP_KEYRESP4_KEYCAL4_MASK (0xFFFFFFFFU) 282 #define SDA_AP_KEYRESP4_KEYCAL4_SHIFT (0U) 283 #define SDA_AP_KEYRESP4_KEYCAL4_WIDTH (32U) 284 #define SDA_AP_KEYRESP4_KEYCAL4(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP4_KEYCAL4_SHIFT)) & SDA_AP_KEYRESP4_KEYCAL4_MASK) 285 /*! @} */ 286 287 /*! @name KEYRESP5 - Key Response 5 register */ 288 /*! @{ */ 289 290 #define SDA_AP_KEYRESP5_KEYCAL5_MASK (0xFFFFFFFFU) 291 #define SDA_AP_KEYRESP5_KEYCAL5_SHIFT (0U) 292 #define SDA_AP_KEYRESP5_KEYCAL5_WIDTH (32U) 293 #define SDA_AP_KEYRESP5_KEYCAL5(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP5_KEYCAL5_SHIFT)) & SDA_AP_KEYRESP5_KEYCAL5_MASK) 294 /*! @} */ 295 296 /*! @name KEYRESP6 - Key Response 6 register */ 297 /*! @{ */ 298 299 #define SDA_AP_KEYRESP6_KEYCAL6_MASK (0xFFFFFFFFU) 300 #define SDA_AP_KEYRESP6_KEYCAL6_SHIFT (0U) 301 #define SDA_AP_KEYRESP6_KEYCAL6_WIDTH (32U) 302 #define SDA_AP_KEYRESP6_KEYCAL6(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP6_KEYCAL6_SHIFT)) & SDA_AP_KEYRESP6_KEYCAL6_MASK) 303 /*! @} */ 304 305 /*! @name KEYRESP7 - Key Response 7 register */ 306 /*! @{ */ 307 308 #define SDA_AP_KEYRESP7_KEYCAL7_MASK (0xFFFFFFFFU) 309 #define SDA_AP_KEYRESP7_KEYCAL7_SHIFT (0U) 310 #define SDA_AP_KEYRESP7_KEYCAL7_WIDTH (32U) 311 #define SDA_AP_KEYRESP7_KEYCAL7(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_KEYRESP7_KEYCAL7_SHIFT)) & SDA_AP_KEYRESP7_KEYCAL7_MASK) 312 /*! @} */ 313 314 /*! @name SDAUIDL - UID Low Register */ 315 /*! @{ */ 316 317 #define SDA_AP_SDAUIDL_SDAUIDL_MASK (0xFFFFFFFFU) 318 #define SDA_AP_SDAUIDL_SDAUIDL_SHIFT (0U) 319 #define SDA_AP_SDAUIDL_SDAUIDL_WIDTH (32U) 320 #define SDA_AP_SDAUIDL_SDAUIDL(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDAUIDL_SDAUIDL_SHIFT)) & SDA_AP_SDAUIDL_SDAUIDL_MASK) 321 /*! @} */ 322 323 /*! @name SDAUIDH - UID High Register */ 324 /*! @{ */ 325 326 #define SDA_AP_SDAUIDH_SDAUIDH_MASK (0xFFFFFFFFU) 327 #define SDA_AP_SDAUIDH_SDAUIDH_SHIFT (0U) 328 #define SDA_AP_SDAUIDH_SDAUIDH_WIDTH (32U) 329 #define SDA_AP_SDAUIDH_SDAUIDH(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDAUIDH_SDAUIDH_SHIFT)) & SDA_AP_SDAUIDH_SDAUIDH_MASK) 330 /*! @} */ 331 332 /*! @name SDASYSRSTS - System reset status register */ 333 /*! @{ */ 334 335 #define SDA_AP_SDASYSRSTS_DESTRUCT_RESET_MASK (0x2U) 336 #define SDA_AP_SDASYSRSTS_DESTRUCT_RESET_SHIFT (1U) 337 #define SDA_AP_SDASYSRSTS_DESTRUCT_RESET_WIDTH (1U) 338 #define SDA_AP_SDASYSRSTS_DESTRUCT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDASYSRSTS_DESTRUCT_RESET_SHIFT)) & SDA_AP_SDASYSRSTS_DESTRUCT_RESET_MASK) 339 340 #define SDA_AP_SDASYSRSTS_SYSTEM_RESET_MASK (0x4U) 341 #define SDA_AP_SDASYSRSTS_SYSTEM_RESET_SHIFT (2U) 342 #define SDA_AP_SDASYSRSTS_SYSTEM_RESET_WIDTH (1U) 343 #define SDA_AP_SDASYSRSTS_SYSTEM_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDASYSRSTS_SYSTEM_RESET_SHIFT)) & SDA_AP_SDASYSRSTS_SYSTEM_RESET_MASK) 344 /*! @} */ 345 346 /*! @name SDASYSRSTC - System Reset Control Register */ 347 /*! @{ */ 348 349 #define SDA_AP_SDASYSRSTC_SYSRESTREQ_MASK (0x10U) 350 #define SDA_AP_SDASYSRSTC_SYSRESTREQ_SHIFT (4U) 351 #define SDA_AP_SDASYSRSTC_SYSRESTREQ_WIDTH (1U) 352 #define SDA_AP_SDASYSRSTC_SYSRESTREQ(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDASYSRSTC_SYSRESTREQ_SHIFT)) & SDA_AP_SDASYSRSTC_SYSRESTREQ_MASK) 353 354 #define SDA_AP_SDASYSRSTC_SYSFUNCREQ_MASK (0x20U) 355 #define SDA_AP_SDASYSRSTC_SYSFUNCREQ_SHIFT (5U) 356 #define SDA_AP_SDASYSRSTC_SYSFUNCREQ_WIDTH (1U) 357 #define SDA_AP_SDASYSRSTC_SYSFUNCREQ(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDASYSRSTC_SYSFUNCREQ_SHIFT)) & SDA_AP_SDASYSRSTC_SYSFUNCREQ_MASK) 358 /*! @} */ 359 360 /*! @name SDARSTCTRL - Reset Control Register */ 361 /*! @{ */ 362 363 #define SDA_AP_SDARSTCTRL_RSTWAITCEB_MASK (0x800U) 364 #define SDA_AP_SDARSTCTRL_RSTWAITCEB_SHIFT (11U) 365 #define SDA_AP_SDARSTCTRL_RSTWAITCEB_WIDTH (1U) 366 #define SDA_AP_SDARSTCTRL_RSTWAITCEB(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTWAITCEB_SHIFT)) & SDA_AP_SDARSTCTRL_RSTWAITCEB_MASK) 367 368 #define SDA_AP_SDARSTCTRL_RSTWAITCEA_MASK (0x1000U) 369 #define SDA_AP_SDARSTCTRL_RSTWAITCEA_SHIFT (12U) 370 #define SDA_AP_SDARSTCTRL_RSTWAITCEA_WIDTH (1U) 371 #define SDA_AP_SDARSTCTRL_RSTWAITCEA(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTWAITCEA_SHIFT)) & SDA_AP_SDARSTCTRL_RSTWAITCEA_MASK) 372 373 #define SDA_AP_SDARSTCTRL_RSTWAITSMU_MASK (0x8000U) 374 #define SDA_AP_SDARSTCTRL_RSTWAITSMU_SHIFT (15U) 375 #define SDA_AP_SDARSTCTRL_RSTWAITSMU_WIDTH (1U) 376 #define SDA_AP_SDARSTCTRL_RSTWAITSMU(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTWAITSMU_SHIFT)) & SDA_AP_SDARSTCTRL_RSTWAITSMU_MASK) 377 378 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS_MASK (0x10000U) 379 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS_SHIFT (16U) 380 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS_WIDTH (1U) 381 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELSPF2_SYS_MASK) 382 383 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE_MASK (0x20000U) 384 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE_SHIFT (17U) 385 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE_WIDTH (1U) 386 #define SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELSPF2_CORE_MASK) 387 388 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C3_MASK (0x100000U) 389 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C3_SHIFT (20U) 390 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C3_WIDTH (1U) 391 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU1_C3_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU1_C3_MASK) 392 393 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C2_MASK (0x200000U) 394 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C2_SHIFT (21U) 395 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C2_WIDTH (1U) 396 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU1_C2_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU1_C2_MASK) 397 398 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C1_MASK (0x400000U) 399 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C1_SHIFT (22U) 400 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C1_WIDTH (1U) 401 #define SDA_AP_SDARSTCTRL_RSTRELRTU1_C1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU1_C1_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU1_C1_MASK) 402 403 #define SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0_MASK (0x800000U) 404 #define SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0_SHIFT (23U) 405 #define SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0_WIDTH (1U) 406 #define SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0_SHIFT)) & SDA_AP_SDARSTCTRL_RSTREL_RTU1_C0_MASK) 407 408 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C3_MASK (0x10000000U) 409 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C3_SHIFT (28U) 410 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C3_WIDTH (1U) 411 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU0_C3_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU0_C3_MASK) 412 413 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C2_MASK (0x20000000U) 414 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C2_SHIFT (29U) 415 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C2_WIDTH (1U) 416 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU0_C2_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU0_C2_MASK) 417 418 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C1_MASK (0x40000000U) 419 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C1_SHIFT (30U) 420 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C1_WIDTH (1U) 421 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU0_C1_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU0_C1_MASK) 422 423 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C0_MASK (0x80000000U) 424 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C0_SHIFT (31U) 425 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C0_WIDTH (1U) 426 #define SDA_AP_SDARSTCTRL_RSTRELRTU0_C0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTCTRL_RSTRELRTU0_C0_SHIFT)) & SDA_AP_SDARSTCTRL_RSTRELRTU0_C0_MASK) 427 /*! @} */ 428 429 /*! @name SDARSTMASK - Reset Control Mask Register */ 430 /*! @{ */ 431 432 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_POR_MASK (0x80000U) 433 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_POR_SHIFT (19U) 434 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_POR_WIDTH (1U) 435 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_POR(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU1_POR_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU1_POR_MASK) 436 437 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C3_MASK (0x100000U) 438 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C3_SHIFT (20U) 439 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C3_WIDTH (1U) 440 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU1_C3_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU1_C3_MASK) 441 442 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C2_MASK (0x200000U) 443 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C2_SHIFT (21U) 444 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C2_WIDTH (1U) 445 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU1_C2_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU1_C2_MASK) 446 447 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C1_MASK (0x400000U) 448 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C1_SHIFT (22U) 449 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C1_WIDTH (1U) 450 #define SDA_AP_SDARSTMASK_RSTMSKRTU1_C1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU1_C1_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU1_C1_MASK) 451 452 #define SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0_MASK (0x800000U) 453 #define SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0_SHIFT (23U) 454 #define SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0_WIDTH (1U) 455 #define SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSK_RTU1_C0_MASK) 456 457 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_POR_MASK (0x8000000U) 458 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_POR_SHIFT (27U) 459 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_POR_WIDTH (1U) 460 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_POR(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU0_POR_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU0_POR_MASK) 461 462 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C3_MASK (0x10000000U) 463 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C3_SHIFT (28U) 464 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C3_WIDTH (1U) 465 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU0_C3_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU0_C3_MASK) 466 467 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C2_MASK (0x20000000U) 468 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C2_SHIFT (29U) 469 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C2_WIDTH (1U) 470 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU0_C2_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU0_C2_MASK) 471 472 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C1_MASK (0x40000000U) 473 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C1_SHIFT (30U) 474 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C1_WIDTH (1U) 475 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU0_C1_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU0_C1_MASK) 476 477 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C0_MASK (0x80000000U) 478 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C0_SHIFT (31U) 479 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C0_WIDTH (1U) 480 #define SDA_AP_SDARSTMASK_RSTMSKRTU0_C0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_SDARSTMASK_RSTMSKRTU0_C0_SHIFT)) & SDA_AP_SDARSTMASK_RSTMSKRTU0_C0_MASK) 481 /*! @} */ 482 483 /*! @name IDR - Identification Register */ 484 /*! @{ */ 485 486 #define SDA_AP_IDR_Type_MASK (0xFU) 487 #define SDA_AP_IDR_Type_SHIFT (0U) 488 #define SDA_AP_IDR_Type_WIDTH (4U) 489 #define SDA_AP_IDR_Type(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_Type_SHIFT)) & SDA_AP_IDR_Type_MASK) 490 491 #define SDA_AP_IDR_Variant_MASK (0xF0U) 492 #define SDA_AP_IDR_Variant_SHIFT (4U) 493 #define SDA_AP_IDR_Variant_WIDTH (4U) 494 #define SDA_AP_IDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_Variant_SHIFT)) & SDA_AP_IDR_Variant_MASK) 495 496 #define SDA_AP_IDR_Class_MASK (0x1E000U) 497 #define SDA_AP_IDR_Class_SHIFT (13U) 498 #define SDA_AP_IDR_Class_WIDTH (4U) 499 #define SDA_AP_IDR_Class(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_Class_SHIFT)) & SDA_AP_IDR_Class_MASK) 500 501 #define SDA_AP_IDR_JEDEC_code_MASK (0xFE0000U) 502 #define SDA_AP_IDR_JEDEC_code_SHIFT (17U) 503 #define SDA_AP_IDR_JEDEC_code_WIDTH (7U) 504 #define SDA_AP_IDR_JEDEC_code(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_JEDEC_code_SHIFT)) & SDA_AP_IDR_JEDEC_code_MASK) 505 506 #define SDA_AP_IDR_JEDEC_bank_MASK (0xF000000U) 507 #define SDA_AP_IDR_JEDEC_bank_SHIFT (24U) 508 #define SDA_AP_IDR_JEDEC_bank_WIDTH (4U) 509 #define SDA_AP_IDR_JEDEC_bank(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_JEDEC_bank_SHIFT)) & SDA_AP_IDR_JEDEC_bank_MASK) 510 511 #define SDA_AP_IDR_REVISION_MASK (0xF0000000U) 512 #define SDA_AP_IDR_REVISION_SHIFT (28U) 513 #define SDA_AP_IDR_REVISION_WIDTH (4U) 514 #define SDA_AP_IDR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_IDR_REVISION_SHIFT)) & SDA_AP_IDR_REVISION_MASK) 515 /*! @} */ 516 517 /*! @name DEVARCH - CoreSight Device Architecture Register */ 518 /*! @{ */ 519 520 #define SDA_AP_DEVARCH_ARCHID_MASK (0xFFFFU) 521 #define SDA_AP_DEVARCH_ARCHID_SHIFT (0U) 522 #define SDA_AP_DEVARCH_ARCHID_WIDTH (16U) 523 #define SDA_AP_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVARCH_ARCHID_SHIFT)) & SDA_AP_DEVARCH_ARCHID_MASK) 524 525 #define SDA_AP_DEVARCH_REVISION_MASK (0xF0000U) 526 #define SDA_AP_DEVARCH_REVISION_SHIFT (16U) 527 #define SDA_AP_DEVARCH_REVISION_WIDTH (4U) 528 #define SDA_AP_DEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVARCH_REVISION_SHIFT)) & SDA_AP_DEVARCH_REVISION_MASK) 529 530 #define SDA_AP_DEVARCH_PRESENT_MASK (0x100000U) 531 #define SDA_AP_DEVARCH_PRESENT_SHIFT (20U) 532 #define SDA_AP_DEVARCH_PRESENT_WIDTH (1U) 533 #define SDA_AP_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVARCH_PRESENT_SHIFT)) & SDA_AP_DEVARCH_PRESENT_MASK) 534 535 #define SDA_AP_DEVARCH_ARCHITECT_MASK (0xFFE00000U) 536 #define SDA_AP_DEVARCH_ARCHITECT_SHIFT (21U) 537 #define SDA_AP_DEVARCH_ARCHITECT_WIDTH (11U) 538 #define SDA_AP_DEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVARCH_ARCHITECT_SHIFT)) & SDA_AP_DEVARCH_ARCHITECT_MASK) 539 /*! @} */ 540 541 /*! @name DEVTYPE - CoreSight Device Type Identifier Register */ 542 /*! @{ */ 543 544 #define SDA_AP_DEVTYPE_MAJOR_MASK (0xFU) 545 #define SDA_AP_DEVTYPE_MAJOR_SHIFT (0U) 546 #define SDA_AP_DEVTYPE_MAJOR_WIDTH (4U) 547 #define SDA_AP_DEVTYPE_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVTYPE_MAJOR_SHIFT)) & SDA_AP_DEVTYPE_MAJOR_MASK) 548 549 #define SDA_AP_DEVTYPE_SUB_MASK (0xF0U) 550 #define SDA_AP_DEVTYPE_SUB_SHIFT (4U) 551 #define SDA_AP_DEVTYPE_SUB_WIDTH (4U) 552 #define SDA_AP_DEVTYPE_SUB(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_DEVTYPE_SUB_SHIFT)) & SDA_AP_DEVTYPE_SUB_MASK) 553 /*! @} */ 554 555 /*! @name PIDR4 - CoreSight Peripheral Identification Register 4 */ 556 /*! @{ */ 557 558 #define SDA_AP_PIDR4_DES_2_MASK (0xFU) 559 #define SDA_AP_PIDR4_DES_2_SHIFT (0U) 560 #define SDA_AP_PIDR4_DES_2_WIDTH (4U) 561 #define SDA_AP_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR4_DES_2_SHIFT)) & SDA_AP_PIDR4_DES_2_MASK) 562 563 #define SDA_AP_PIDR4_SIZE_MASK (0xF0U) 564 #define SDA_AP_PIDR4_SIZE_SHIFT (4U) 565 #define SDA_AP_PIDR4_SIZE_WIDTH (4U) 566 #define SDA_AP_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR4_SIZE_SHIFT)) & SDA_AP_PIDR4_SIZE_MASK) 567 /*! @} */ 568 569 /*! @name PIDR0 - CoreSight Peripheral Identification Register 0 */ 570 /*! @{ */ 571 572 #define SDA_AP_PIDR0_PART_0_MASK (0xFFU) 573 #define SDA_AP_PIDR0_PART_0_SHIFT (0U) 574 #define SDA_AP_PIDR0_PART_0_WIDTH (8U) 575 #define SDA_AP_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR0_PART_0_SHIFT)) & SDA_AP_PIDR0_PART_0_MASK) 576 /*! @} */ 577 578 /*! @name PIDR1 - CoreSight Peripheral Identification Register 1 */ 579 /*! @{ */ 580 581 #define SDA_AP_PIDR1_PART_1_MASK (0xFU) 582 #define SDA_AP_PIDR1_PART_1_SHIFT (0U) 583 #define SDA_AP_PIDR1_PART_1_WIDTH (4U) 584 #define SDA_AP_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR1_PART_1_SHIFT)) & SDA_AP_PIDR1_PART_1_MASK) 585 586 #define SDA_AP_PIDR1_DES_0_MASK (0xF0U) 587 #define SDA_AP_PIDR1_DES_0_SHIFT (4U) 588 #define SDA_AP_PIDR1_DES_0_WIDTH (4U) 589 #define SDA_AP_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR1_DES_0_SHIFT)) & SDA_AP_PIDR1_DES_0_MASK) 590 /*! @} */ 591 592 /*! @name PIDR2 - CoreSight Peripheral Identification Register 2 */ 593 /*! @{ */ 594 595 #define SDA_AP_PIDR2_DES_1_MASK (0x7U) 596 #define SDA_AP_PIDR2_DES_1_SHIFT (0U) 597 #define SDA_AP_PIDR2_DES_1_WIDTH (3U) 598 #define SDA_AP_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR2_DES_1_SHIFT)) & SDA_AP_PIDR2_DES_1_MASK) 599 600 #define SDA_AP_PIDR2_JEDEC_MASK (0x8U) 601 #define SDA_AP_PIDR2_JEDEC_SHIFT (3U) 602 #define SDA_AP_PIDR2_JEDEC_WIDTH (1U) 603 #define SDA_AP_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR2_JEDEC_SHIFT)) & SDA_AP_PIDR2_JEDEC_MASK) 604 605 #define SDA_AP_PIDR2_REVISION_MASK (0xF0U) 606 #define SDA_AP_PIDR2_REVISION_SHIFT (4U) 607 #define SDA_AP_PIDR2_REVISION_WIDTH (4U) 608 #define SDA_AP_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR2_REVISION_SHIFT)) & SDA_AP_PIDR2_REVISION_MASK) 609 /*! @} */ 610 611 /*! @name PIDR3 - CoreSight Peripheral Identification Register 3 */ 612 /*! @{ */ 613 614 #define SDA_AP_PIDR3_CMOD_MASK (0xFU) 615 #define SDA_AP_PIDR3_CMOD_SHIFT (0U) 616 #define SDA_AP_PIDR3_CMOD_WIDTH (4U) 617 #define SDA_AP_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR3_CMOD_SHIFT)) & SDA_AP_PIDR3_CMOD_MASK) 618 619 #define SDA_AP_PIDR3_REVAND_MASK (0xF0U) 620 #define SDA_AP_PIDR3_REVAND_SHIFT (4U) 621 #define SDA_AP_PIDR3_REVAND_WIDTH (4U) 622 #define SDA_AP_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_PIDR3_REVAND_SHIFT)) & SDA_AP_PIDR3_REVAND_MASK) 623 /*! @} */ 624 625 /*! @name CIDR0 - CoreSight Component Identification Register 0 */ 626 /*! @{ */ 627 628 #define SDA_AP_CIDR0_PRMBL_0_MASK (0xFFU) 629 #define SDA_AP_CIDR0_PRMBL_0_SHIFT (0U) 630 #define SDA_AP_CIDR0_PRMBL_0_WIDTH (8U) 631 #define SDA_AP_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_CIDR0_PRMBL_0_SHIFT)) & SDA_AP_CIDR0_PRMBL_0_MASK) 632 /*! @} */ 633 634 /*! @name CIDR1 - CoreSight Component Identification Register 1 */ 635 /*! @{ */ 636 637 #define SDA_AP_CIDR1_PRMBL_1_MASK (0xFU) 638 #define SDA_AP_CIDR1_PRMBL_1_SHIFT (0U) 639 #define SDA_AP_CIDR1_PRMBL_1_WIDTH (4U) 640 #define SDA_AP_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_CIDR1_PRMBL_1_SHIFT)) & SDA_AP_CIDR1_PRMBL_1_MASK) 641 642 #define SDA_AP_CIDR1_CLASS_MASK (0xF0U) 643 #define SDA_AP_CIDR1_CLASS_SHIFT (4U) 644 #define SDA_AP_CIDR1_CLASS_WIDTH (4U) 645 #define SDA_AP_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_CIDR1_CLASS_SHIFT)) & SDA_AP_CIDR1_CLASS_MASK) 646 /*! @} */ 647 648 /*! @name CIDR2 - CoreSight Component Identification Register 2 */ 649 /*! @{ */ 650 651 #define SDA_AP_CIDR2_PRMBL_2_MASK (0xFFU) 652 #define SDA_AP_CIDR2_PRMBL_2_SHIFT (0U) 653 #define SDA_AP_CIDR2_PRMBL_2_WIDTH (8U) 654 #define SDA_AP_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_CIDR2_PRMBL_2_SHIFT)) & SDA_AP_CIDR2_PRMBL_2_MASK) 655 /*! @} */ 656 657 /*! @name CIDR3 - CoreSight Component Identification Register 3 */ 658 /*! @{ */ 659 660 #define SDA_AP_CIDR3_PRMBL_3_MASK (0xFFU) 661 #define SDA_AP_CIDR3_PRMBL_3_SHIFT (0U) 662 #define SDA_AP_CIDR3_PRMBL_3_WIDTH (8U) 663 #define SDA_AP_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << SDA_AP_CIDR3_PRMBL_3_SHIFT)) & SDA_AP_CIDR3_PRMBL_3_MASK) 664 /*! @} */ 665 666 /*! 667 * @} 668 */ /* end of group SDA_AP_Register_Masks */ 669 670 /*! 671 * @} 672 */ /* end of group SDA_AP_Peripheral_Access_Layer */ 673 674 #endif /* #if !defined(S32Z2_SDA_AP_H_) */ 675
