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Searched refs:SCG_UPLLCSR_UPLLSEL_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53874 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
53880 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53832 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
53838 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h65393 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
65399 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
DMCXN546_cm33_core1.h65393 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
65399 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h65393 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
65399 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
DMCXN547_cm33_core1.h65393 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
65399 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h66140 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
66146 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
DMCXN947_cm33_core0.h66140 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
66146 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h66140 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
66146 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
DMCXN946_cm33_core1.h66140 #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) macro
66146 … (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)