Home
last modified time | relevance | path

Searched refs:SCG_SPLLDIV_SPLLDIV2 (Results 1 – 25 of 27) sorted by relevance

12

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142W_SCG.h456 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
DS32K142_SCG.h480 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
DS32K146_SCG.h480 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
DS32K144_SCG.h480 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
DS32K148_SCG.h480 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
DS32K144W_SCG.h456 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h1270 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h1270 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h1264 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h1334 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1074 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h1334 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1074 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h1795 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1426 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h1795 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
Dfsl_clock.c1426 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h16245 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h15267 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h15267 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h17251 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h17245 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDI… macro

12