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Searched refs:SCG_SPLLCSR_SPLLVLD_MASK (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142W_SCG.h429 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
432 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
DS32K142_SCG.h453 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
456 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
DS32K146_SCG.h453 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
456 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
DS32K144_SCG.h453 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
456 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
DS32K148_SCG.h453 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
456 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
DS32K144W_SCG.h429 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
432 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c1044 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1121 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
Dfsl_clock.h1339 return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.c1044 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1121 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
Dfsl_clock.h1333 return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.c1044 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1121 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
Dfsl_clock.h1339 return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.c1084 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1161 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
Dfsl_clock.h1403 return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.c1084 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1161 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
Dfsl_clock.h1403 return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h1888 return ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) == SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
Dfsl_clock.c1437 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1521 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h1888 return ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) == SCG_SPLLCSR_SPLLVLD_MASK); in CLOCK_IsSysPllValid()
Dfsl_clock.c1437 while (0UL == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) in CLOCK_InitSysPll()
1521 if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) != 0UL) /* System PLL is valid. */ in CLOCK_GetSysPllFreq()
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Pll.c200 … SpllStatus = (((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) >> SCG_SPLLCSR_SPLLVLD_SHIFT)); in Clock_Ip_CompleteSpll()
DClock_Ip_Frequency.c733 …return (((((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) >> SCG_SPLLCSR_SPLLVLD_SHIFT)) != 0U )? Sp… in get_SPLL_CLK_Frequency()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h16190 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
16196 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h15212 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
15218 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h15212 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) macro
15218 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)

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