Searched refs:SCG_SPLLCSR_SPLLEN_MASK (Results 1 – 25 of 30) sorted by relevance
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194 if ((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLEN_MASK) != 0U) in Clock_Ip_CompleteSpll()268 IP_SCG->SPLLCSR &= (~((uint32)SCG_SPLLCSR_SPLLEN_MASK)); in Clock_Ip_ResetSpll_TrustedCall()342 IP_SCG->SPLLCSR &= (~((uint32)SCG_SPLLCSR_SPLLEN_MASK)); in Clock_Ip_DisableSpll_TrustedCall()
619 …SpllConfiguration.Enable = (uint16)(IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLEN_MASK) >> SCG_SPLLCSR_SPLL… in getSpllConfig()
730 …SpllFreq &= Clock_Ip_u32EnableClock[((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLEN_MASK) >> SCG_SPLLCSR_SP… in get_SPLL_CLK_Frequency()
409 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) macro412 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
433 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) macro436 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
611 kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK, /*!< Enable SPLL clock. */
1041 SCG->SPLLCSR = (uint32_t)SCG_SPLLCSR_SPLLEN_MASK | config->enableMode; in CLOCK_InitSysPll()
605 kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK, /*!< Enable SPLL clock. */
609 kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK, /*!< Enable SPLL clock. */
1081 SCG->SPLLCSR = (uint32_t)SCG_SPLLCSR_SPLLEN_MASK | config->enableMode; in CLOCK_InitSysPll()
765 kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK, /*!< Enable SPLL clock. */
1434 SCG->SPLLCSR = (uint32_t)SCG_SPLLCSR_SPLLEN_MASK | config->enableMode; in CLOCK_InitSysPll()
16150 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) macro16156 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
15172 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) macro15178 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
