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Searched refs:SCG_SPLLCSR_SPLLCLKEN_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c1783 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
1807 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c1783 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
1807 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c2197 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2221 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c2197 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2221 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c2197 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2221 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c2197 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2221 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53477 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
53483 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53435 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
53441 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h65020 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65026 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
DMCXN546_cm33_core1.h65020 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65026 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h65020 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65026 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
DMCXN547_cm33_core1.h65020 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65026 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65767 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65773 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
DMCXN947_cm33_core0.h65767 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65773 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65767 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65773 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
DMCXN946_cm33_core1.h65767 #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) macro
65773 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)