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Searched refs:SCG_SOSCDIV_SOSCDIV1_MASK (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_SCG.h263 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
266 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K118_SCG.h263 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
266 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K142W_SCG.h267 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
270 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K142_SCG.h291 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
294 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K146_SCG.h291 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
294 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K144_SCG.h291 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
294 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K148_SCG.h291 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
294 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
DS32K144W_SCG.h267 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
270 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c33 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h924 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c51 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h924 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c51 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h918 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c51 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h983 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c51 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h983 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c51 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h1200 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c64 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h1200 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
Dfsl_clock.c64 #define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV…
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Frequency.c768 …uint32 DivValue = Clock_Ip_au8DividerMappingValue[((IP_SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >… in get_SOSCDIV1_CLK_Frequency()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h15817 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) macro
15829 … (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)

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