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Searched refs:SCG_LPFLLDIV_LPFLLDIV2_VAL (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
908 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c44 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
837 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
885 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.c35 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
902 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
908 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.c35 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
902 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
908 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
885 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
885 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
910 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
956 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L… macro
956 divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; in CLOCK_GetLpFllAsyncFreq()