Home
last modified time | relevance | path

Searched refs:SCG_LPFLLDIV_LPFLLDIV2 (Results 1 – 25 of 37) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h1142 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h1138 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h1130 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h1167 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h1216 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.h1216 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c830 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.h1168 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h1224 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.h1223 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c830 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.h1165 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c784 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.h1223 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c718 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | in CLOCK_InitLpFll()
Dfsl_clock.h1311 reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); in CLOCK_SetLpFllAsyncClkDiv()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h10295 #define SCG_LPFLLDIV_LPFLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLL… macro

12