Searched refs:SCG_HCCR_DIVCORE_MASK (Results 1 – 18 of 18) sorted by relevance
229 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro232 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
576 RegValue &= ~SCG_HCCR_DIVCORE_MASK; in Clock_Ip_SetScgHsrunDivcore_TrustedCall()
793 …ividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->HCCR & SCG_HCCR_DIVCORE_MASK) >> SCG_HC… in getCoreDividerConfig()
12311 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro12331 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
12315 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro12335 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
12313 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro12333 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
15674 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro15694 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
14636 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro14656 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
16680 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro16700 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
16674 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro16694 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
17604 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro17624 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
17714 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro17734 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
28695 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro28715 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
28696 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) macro28716 … (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
