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Searched refs:SCG_FIRCCSR_FIRCSEL_MASK (Results 1 – 25 of 75) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_SCG.h373 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
376 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K118_SCG.h373 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
376 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K142W_SCG.h377 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
380 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K142_SCG.h401 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
404 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K146_SCG.h401 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
404 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K144_SCG.h401 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
404 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K148_SCG.h401 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
404 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
DS32K144W_SCG.h377 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) macro
380 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c580 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) == SCG_FIRCCSR_FIRCSEL_MASK) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c579 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) == SCG_FIRCCSR_FIRCSEL_MASK) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c579 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) == SCG_FIRCCSR_FIRCSEL_MASK) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.c674 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c590 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.c654 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.c670 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.c674 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.c670 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.c674 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.c654 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.c654 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.c673 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.c719 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.c719 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_IntOsc.c627 if ((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCSEL_MASK) != 0U) in Clock_Ip_SetFirc_TrustedCall()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c785 if ((reg & SCG_FIRCCSR_FIRCSEL_MASK) != 0UL) in CLOCK_DeinitFirc()

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