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Searched refs:SCG_FIRCCSR_FIRCERR_IE_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h25049 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
25055 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h25049 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
25055 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h25049 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
25055 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h25049 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
25055 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h32317 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32323 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h32317 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32323 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h32317 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32323 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h32939 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32945 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h32939 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32945 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h32939 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
32945 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h52946 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
52952 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h52904 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
52910 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64513 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
64519 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
DMCXN546_cm33_core1.h64513 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
64519 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64513 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
64519 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
DMCXN547_cm33_core1.h64513 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
64519 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65260 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
65266 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
DMCXN947_cm33_core0.h65260 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
65266 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65260 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
65266 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
DMCXN946_cm33_core1.h65260 #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) macro
65266 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)