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Searched refs:SCG_FIRCCSR_FIRCEN_MASK (Results 1 – 25 of 115) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_IntOsc.c644 IP_SCG->FIRCCSR &= (~((uint32)SCG_FIRCCSR_FIRCEN_MASK)); in Clock_Ip_SetFirc_TrustedCall()
685 IP_SCG->FIRCCSR &= (~((uint32)SCG_FIRCCSR_FIRCEN_MASK)); in Clock_Ip_SetFirc_TrustedCall()
746 IP_SCG->FIRCCSR &= ~SCG_FIRCCSR_FIRCEN_MASK; in Clock_Ip_DisableFirc_TrustedCall()
DClock_Ip_Specific.c480 if ((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) in Clock_Ip_SpecificPlatformInitClock()
552 …FircConfiguration.Enable = (uint16)(IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) >> SCG_FIRCCSR_FIRC… in getFircConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1157 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1157 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1157 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1157 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_SCG.h353 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
356 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K118_SCG.h353 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
356 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K142W_SCG.h357 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
360 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K142_SCG.h381 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
384 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K146_SCG.h381 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
384 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K144_SCG.h381 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
384 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K148_SCG.h381 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
384 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
DS32K144W_SCG.h357 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) macro
360 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/drivers/
Dfsl_clock.c243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) in CLOCK_EnableUsbfsClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c554 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c553 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c553 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h483 kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK, /*!< Enable FIRC clock. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h479 kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK, /*!< Enable FIRC clock. */

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