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Searched refs:SCG_CSR_DIVSLOW_MASK (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_SCG.h143 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
146 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K118_SCG.h143 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
146 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K142W_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K142_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K146_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K144_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K148_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DS32K144W_SCG.h147 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
150 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Frequency.c854 …return get_CORE_CLK_Frequency() / (((IP_SCG->CSR & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT)… in get_SLOW_CLK_Frequency()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h9678 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
9698 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h9680 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
9700 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h10517 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
10537 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h12199 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12219 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h12103 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12123 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h12205 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12225 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h12202 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12222 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h12458 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12478 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h12107 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12127 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h12461 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12481 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h12105 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
12125 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h15378 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
15398 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h14428 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
14448 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h14428 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
14448 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h16384 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
16404 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h16378 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
16398 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)

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