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Searched refs:SCG_APLLSSCG1_SS_MDIV_MSB_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c2191 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2546 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c2191 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2546 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c2618 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2973 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c2618 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2973 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c2618 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2973 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c2618 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2973 mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPllMMultFromSetup()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53382 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
53385 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53340 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
53343 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64925 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
64928 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
DMCXN546_cm33_core1.h64925 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
64928 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64925 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
64928 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
DMCXN547_cm33_core1.h64925 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
64928 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65672 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
65675 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
DMCXN947_cm33_core0.h65672 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
65675 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65672 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
65675 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
DMCXN946_cm33_core1.h65672 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) macro
65675 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)