Searched refs:SCG_APLLSSCG1_SEL_SS_MDIV_MASK (Results 1 – 16 of 16) sorted by relevance
2185 if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPll0MMult()2431 pSetup->pllsscg[1] &= ~SCG_APLLSSCG1_SEL_SS_MDIV_MASK; in CLOCK_GetPllConfigInternal()2450 …llsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_APLLSSCG1_SEL_SS_MDIV_MASK; in CLOCK_GetPllConfigInternal()2540 if ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPllMMultFromSetup()
2612 if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPll0MMult()2858 pSetup->pllsscg[1] &= ~SCG_APLLSSCG1_SEL_SS_MDIV_MASK; in CLOCK_GetPllConfigInternal()2877 …llsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_APLLSSCG1_SEL_SS_MDIV_MASK; in CLOCK_GetPllConfigInternal()2967 if ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPllMMultFromSetup()
53421 #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) macro53427 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK)
53379 #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) macro53385 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK)
64964 #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) macro64970 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK)
65711 #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) macro65717 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK)
