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Searched refs:SCG_APLLSSCG0_SS_MDIV_LSB_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53373 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
53376 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53331 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
53334 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64916 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
64919 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
DMCXN546_cm33_core1.h64916 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
64919 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64916 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
64919 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
DMCXN547_cm33_core1.h64916 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
64919 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65663 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
65666 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
DMCXN947_cm33_core0.h65663 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
65666 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65663 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
65666 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
DMCXN946_cm33_core1.h65663 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) macro
65666 …(((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)