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Searched refs:SCG0 (Results 1 – 25 of 67) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c151 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
154 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
157 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
162 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
165 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
203 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
209 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
215 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_SetupExtClocking()
218 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c151 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
154 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
157 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
162 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
165 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
203 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
209 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
215 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_SetupExtClocking()
218 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c153 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
156 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
161 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
164 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
167 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
205 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
211 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtClocking()
212 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtClocking()
218 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c153 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
156 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
161 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
164 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
167 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
205 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
211 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtClocking()
212 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtClocking()
218 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c153 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
156 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
161 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
164 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
167 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
205 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
211 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtClocking()
212 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtClocking()
218 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c153 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
156 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
161 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
164 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
167 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
205 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
211 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtClocking()
212 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtClocking()
218 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
Dsystem_MCIMX7U3_cm4.c168 switch (SCG0->CSR & SCG_CSR_SCS_MASK) in SystemCoreClockUpdate()
176 SCGOUTClock = ((0u == (SCG0->SIRCCFG & SCG_SIRCCFG_RANGE_MASK)) ? 4000000u : 16000000u); in SystemCoreClockUpdate()
180 …SCGOUTClock = 48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * … in SystemCoreClockUpdate()
189 SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ : in SystemCoreClockUpdate()
190 … (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u); in SystemCoreClockUpdate()
191 SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u; in SystemCoreClockUpdate()
192 SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)]; in SystemCoreClockUpdate()
194 if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK)) in SystemCoreClockUpdate()
197 switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) in SystemCoreClockUpdate()
201 … ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD0_MASK) >> SCG_SPLLPFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
Dsystem_MCIMX7U5_cm4.c169 switch (SCG0->CSR & SCG_CSR_SCS_MASK) in SystemCoreClockUpdate()
177 SCGOUTClock = ((0u == (SCG0->SIRCCFG & SCG_SIRCCFG_RANGE_MASK)) ? 4000000u : 16000000u); in SystemCoreClockUpdate()
181 …SCGOUTClock = 48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * … in SystemCoreClockUpdate()
190 SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ : in SystemCoreClockUpdate()
191 … (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u); in SystemCoreClockUpdate()
192 SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u; in SystemCoreClockUpdate()
193 SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)]; in SystemCoreClockUpdate()
195 if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK)) in SystemCoreClockUpdate()
198 switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK) in SystemCoreClockUpdate()
202 … ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD0_MASK) >> SCG_SPLLPFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); in CLOCK_SetupFROHFClocking()
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c41 #define SCG_FIRCCFG_RANGE_VAL ((CLOCK_REG(&SCG0->FIRCCFG) & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_…
336 CLOCK_REG(&SCG0->SOSCCSR) = (uint32_t)config->enableMode | SCG_SOSCCSR_SOSCEN_MASK; in CLOCK_InitSysOsc()
341 while ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) != SCG_SOSCCSR_SOSCVLD_MASK) in CLOCK_InitSysOsc()
361 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_DeinitSysOsc()
375 CLOCK_REG(&SCG0->SOSCCSR) = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_DeinitSysOsc()
387 if ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) == in CLOCK_GetSysOscFreq()
428 CLOCK_REG(&SCG0->SIRCCSR) = (uint32_t)config->enableMode; in CLOCK_InitSirc()
438 while ((CLOCK_REG(&SCG0->SIRCCSR) & SCG_SIRCCSR_SIRCVLD_MASK) != SCG_SIRCCSR_SIRCVLD_MASK) in CLOCK_InitSirc()
458 uint32_t reg = CLOCK_REG(&SCG0->SIRCCSR); in CLOCK_DeinitSirc()
472 CLOCK_REG(&SCG0->SIRCCSR) = 0U; in CLOCK_DeinitSirc()
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Dfsl_clock.h863 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
883 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
896 CLOCK_REG(&SCG0->CLKOUTCNFG) = SCG_CLKOUTCNFG_CLKOUTSEL(setting); in CLOCK_SetClkOutSel()
948 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCERR_MASK); in CLOCK_IsSysOscErr()
956 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_ClearSysOscErr()
969 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_SetSysOscMonitorMode()
975 CLOCK_REG(&SCG0->SOSCCSR) = reg; in CLOCK_SetSysOscMonitorMode()
985 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK); in CLOCK_IsSysOscValid()
993 CLOCK_REG(&SCG0->SOSCCSR) &= ~(SCG_SOSCCSR_LK_MASK); in CLOCK_UnlockSysOscControlStatusReg()
1001 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_LK_MASK; in CLOCK_LockSysOscControlStatusReg()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c41 #define SCG_FIRCCFG_RANGE_VAL ((CLOCK_REG(&SCG0->FIRCCFG) & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_…
335 CLOCK_REG(&SCG0->SOSCCSR) = (uint32_t)config->enableMode | SCG_SOSCCSR_SOSCEN_MASK; in CLOCK_InitSysOsc()
340 while ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) != SCG_SOSCCSR_SOSCVLD_MASK) in CLOCK_InitSysOsc()
360 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_DeinitSysOsc()
374 CLOCK_REG(&SCG0->SOSCCSR) = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_DeinitSysOsc()
386 if ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) == in CLOCK_GetSysOscFreq()
427 CLOCK_REG(&SCG0->SIRCCSR) = (uint32_t)config->enableMode; in CLOCK_InitSirc()
437 while ((CLOCK_REG(&SCG0->SIRCCSR) & SCG_SIRCCSR_SIRCVLD_MASK) != SCG_SIRCCSR_SIRCVLD_MASK) in CLOCK_InitSirc()
457 uint32_t reg = CLOCK_REG(&SCG0->SIRCCSR); in CLOCK_DeinitSirc()
471 CLOCK_REG(&SCG0->SIRCCSR) = 0U; in CLOCK_DeinitSirc()
[all …]
Dfsl_clock.h801 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
821 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
834 CLOCK_REG(&SCG0->CLKOUTCNFG) = SCG_CLKOUTCNFG_CLKOUTSEL(setting); in CLOCK_SetClkOutSel()
886 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCERR_MASK); in CLOCK_IsSysOscErr()
894 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_ClearSysOscErr()
907 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_SetSysOscMonitorMode()
913 CLOCK_REG(&SCG0->SOSCCSR) = reg; in CLOCK_SetSysOscMonitorMode()
923 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK); in CLOCK_IsSysOscValid()
931 CLOCK_REG(&SCG0->SOSCCSR) &= ~(SCG_SOSCCSR_LK_MASK); in CLOCK_UnlockSysOscControlStatusReg()
939 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_LK_MASK; in CLOCK_LockSysOscControlStatusReg()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c41 #define SCG_FIRCCFG_RANGE_VAL ((CLOCK_REG(&SCG0->FIRCCFG) & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_…
335 CLOCK_REG(&SCG0->SOSCCSR) = (uint32_t)config->enableMode | SCG_SOSCCSR_SOSCEN_MASK; in CLOCK_InitSysOsc()
340 while ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) != SCG_SOSCCSR_SOSCVLD_MASK) in CLOCK_InitSysOsc()
360 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_DeinitSysOsc()
374 CLOCK_REG(&SCG0->SOSCCSR) = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_DeinitSysOsc()
386 if ((CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK) == in CLOCK_GetSysOscFreq()
427 CLOCK_REG(&SCG0->SIRCCSR) = (uint32_t)config->enableMode; in CLOCK_InitSirc()
437 while ((CLOCK_REG(&SCG0->SIRCCSR) & SCG_SIRCCSR_SIRCVLD_MASK) != SCG_SIRCCSR_SIRCVLD_MASK) in CLOCK_InitSirc()
457 uint32_t reg = CLOCK_REG(&SCG0->SIRCCSR); in CLOCK_DeinitSirc()
471 CLOCK_REG(&SCG0->SIRCCSR) = 0U; in CLOCK_DeinitSirc()
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Dfsl_clock.h801 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
821 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
834 CLOCK_REG(&SCG0->CLKOUTCNFG) = SCG_CLKOUTCNFG_CLKOUTSEL(setting); in CLOCK_SetClkOutSel()
886 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCERR_MASK); in CLOCK_IsSysOscErr()
894 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_ClearSysOscErr()
907 uint32_t reg = CLOCK_REG(&SCG0->SOSCCSR); in CLOCK_SetSysOscMonitorMode()
913 CLOCK_REG(&SCG0->SOSCCSR) = reg; in CLOCK_SetSysOscMonitorMode()
923 return (bool)(CLOCK_REG(&SCG0->SOSCCSR) & SCG_SOSCCSR_SOSCVLD_MASK); in CLOCK_IsSysOscValid()
931 CLOCK_REG(&SCG0->SOSCCSR) &= ~(SCG_SOSCCSR_LK_MASK); in CLOCK_UnlockSysOscControlStatusReg()
939 CLOCK_REG(&SCG0->SOSCCSR) |= SCG_SOSCCSR_LK_MASK; in CLOCK_LockSysOscControlStatusReg()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c274 SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCLPEN_MASK | SCG_SOSCCSR_SOSCSTEN_MASK; in BOARD_InitClock()
275 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCLPEN_MASK | SCG_FIRCCSR_FIRCSTEN_MASK; in BOARD_InitClock()
276 SCG0->SIRCCSR |= SCG_SIRCCSR_SIRCLPEN_MASK | SCG_SIRCCSR_SIRCSTEN_MASK; in BOARD_InitClock()
307 BOARD_SetRunMode(SCG0, *config, qspi, kCLOCK_Qspi, in BOARD_BootClockVLPR()
349 BOARD_SetRunMode(SCG0, *config, qspi, kCLOCK_Qspi, in BOARD_BootClockRUN()
366 BOARD_SetRunMode(SCG0, *config, qspi, kCLOCK_Qspi, in BOARD_BootClockRUN()
401 BOARD_SetRunMode(SCG0, *config, qspi, kCLOCK_Qspi, in BOARD_BootClockHSRUN()
419 BOARD_SetRunMode(SCG0, *config, qspi, kCLOCK_Qspi, in BOARD_BootClockHSRUN()

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