Home
last modified time | relevance | path

Searched refs:SCB_CFSR_MEMFAULTSR_Pos (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm4.h622 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
626 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB …
629 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB …
632 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB …
635 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB …
638 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB …
641 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB …
Dcore_cm7.h676 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
680 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB …
683 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB …
686 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB …
689 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB …
692 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB …
695 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB …
Dcore_cm33.h745 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
749 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB …
752 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB …
755 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB …
758 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB …
761 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB …
764 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB …
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_sc300.h556 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_cm3.h559 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_cm4.h617 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_armv8mml.h737 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_cm35p.h737 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_cm7.h670 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_cm33.h737 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro
Dcore_armv81mml.h746 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB … macro