1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SBSW.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SBSW 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SBSW_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SBSW_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SBSW Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SBSW_Peripheral_Access_Layer SBSW Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SBSW - Size of Registers Arrays */ 72 #define SBSW_TMC_COUNT 32u 73 #define SBSW_AUT_COUNT 32u 74 75 /** SBSW - Register Layout Typedef */ 76 typedef struct { 77 __O uint32_t TMC_CONFIG_UNLOCK; /**< TMC Configuration Unlock, offset: 0x0 */ 78 __O uint32_t TMWDP_CONFIG_UNLOCK; /**< TMWDP Configuration Unlock, offset: 0x4 */ 79 __I uint32_t TMC_CONFIG_STATUS; /**< TMC Configuration Status, offset: 0x8 */ 80 __I uint32_t TMWDP_CONFIG_STATUS; /**< TMWDP Configuration Status, offset: 0xC */ 81 __IO uint32_t DEBUG_MODE; /**< Debug Mode, offset: 0x10 */ 82 __I uint32_t TMC_FAULT_STATUS; /**< TMC Fault Status, offset: 0x14 */ 83 __I uint32_t TMWDP_FAULT_STATUS; /**< TMWDP Fault Status, offset: 0x18 */ 84 uint8_t RESERVED_0[4]; 85 struct SBSW_TMC { /* offset: 0x20, array step: 0x20 */ 86 __IO uint32_t CONFIG; /**< TMC Configuration, array offset: 0x20, array step: 0x20 */ 87 __IO uint32_t DISTANCE; /**< TMC Distance, array offset: 0x24, array step: 0x20 */ 88 __IO uint32_t TIMEOUT; /**< TMC Timeout, array offset: 0x28, array step: 0x20 */ 89 __IO uint32_t CONTROL; /**< TMC Control, array offset: 0x2C, array step: 0x20 */ 90 __IO uint32_t R0; /**< TMC R0 Data, array offset: 0x30, array step: 0x20 */ 91 __IO uint32_t R1; /**< TMC R1 Data, array offset: 0x34, array step: 0x20 */ 92 __IO uint32_t STATUS; /**< TMC Status, array offset: 0x38, array step: 0x20 */ 93 __I uint32_t TIMER; /**< TMC Timer, array offset: 0x3C, array step: 0x20 */ 94 } TMC[SBSW_TMC_COUNT]; 95 __IO uint32_t TMWDP_CONFIG_ADDR; /**< TMWDP Configuration Address, offset: 0x420 */ 96 __IO uint32_t TMWDP_CONTROL; /**< TMWDP Control, offset: 0x424 */ 97 __I uint32_t TMWDP_STATUS; /**< TMWDP Status, offset: 0x428 */ 98 __I uint32_t TMWDP_AUTOMATA_STATUS; /**< TMWDP Automata Status, offset: 0x42C */ 99 __I uint32_t TMWDP_AUTOMATA_ILLGL_TRANS; /**< TMWDP Automata Illegal Transition, offset: 0x430 */ 100 __I uint32_t TMWDP_AUTOMATA_TIME_VIOLATION; /**< TMWDP Automata Time Violation, offset: 0x434 */ 101 uint8_t RESERVED_1[24]; 102 struct SBSW_AUT { /* offset: 0x450, array step: 0x8 */ 103 __I uint32_t STATUS; /**< TMWDP Automaton Status, array offset: 0x450, array step: 0x8 */ 104 __IO uint32_t PRGS_REQ; /**< TMWDP Automaton Progress Request, array offset: 0x454, array step: 0x8 */ 105 } AUT[SBSW_AUT_COUNT]; 106 uint8_t RESERVED_2[2732]; 107 __IO uint32_t TC_ID; /**< TMWDP Core Domain ID, offset: 0xFFC */ 108 } SBSW_Type, *SBSW_MemMapPtr; 109 110 /** Number of instances of the SBSW module. */ 111 #define SBSW_INSTANCE_COUNT (1u) 112 113 /* SBSW - Peripheral instance base addresses */ 114 /** Peripheral SMU__SBSW base address */ 115 #define IP_SMU__SBSW_BASE (0x45290000u) 116 /** Peripheral SMU__SBSW base pointer */ 117 #define IP_SMU__SBSW ((SBSW_Type *)IP_SMU__SBSW_BASE) 118 /** Array initializer of SBSW peripheral base addresses */ 119 #define IP_SBSW_BASE_ADDRS { IP_SMU__SBSW_BASE } 120 /** Array initializer of SBSW peripheral base pointers */ 121 #define IP_SBSW_BASE_PTRS { IP_SMU__SBSW } 122 123 /* ---------------------------------------------------------------------------- 124 -- SBSW Register Masks 125 ---------------------------------------------------------------------------- */ 126 127 /*! 128 * @addtogroup SBSW_Register_Masks SBSW Register Masks 129 * @{ 130 */ 131 132 /*! @name TMC_CONFIG_UNLOCK - TMC Configuration Unlock */ 133 /*! @{ */ 134 135 #define SBSW_TMC_CONFIG_UNLOCK_KEY_MASK (0xFFFFFFFFU) 136 #define SBSW_TMC_CONFIG_UNLOCK_KEY_SHIFT (0U) 137 #define SBSW_TMC_CONFIG_UNLOCK_KEY_WIDTH (32U) 138 #define SBSW_TMC_CONFIG_UNLOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_CONFIG_UNLOCK_KEY_SHIFT)) & SBSW_TMC_CONFIG_UNLOCK_KEY_MASK) 139 /*! @} */ 140 141 /*! @name TMWDP_CONFIG_UNLOCK - TMWDP Configuration Unlock */ 142 /*! @{ */ 143 144 #define SBSW_TMWDP_CONFIG_UNLOCK_KEY_MASK (0xFFFFFFFFU) 145 #define SBSW_TMWDP_CONFIG_UNLOCK_KEY_SHIFT (0U) 146 #define SBSW_TMWDP_CONFIG_UNLOCK_KEY_WIDTH (32U) 147 #define SBSW_TMWDP_CONFIG_UNLOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_CONFIG_UNLOCK_KEY_SHIFT)) & SBSW_TMWDP_CONFIG_UNLOCK_KEY_MASK) 148 /*! @} */ 149 150 /*! @name TMC_CONFIG_STATUS - TMC Configuration Status */ 151 /*! @{ */ 152 153 #define SBSW_TMC_CONFIG_STATUS_STATUS_MASK (0x1U) 154 #define SBSW_TMC_CONFIG_STATUS_STATUS_SHIFT (0U) 155 #define SBSW_TMC_CONFIG_STATUS_STATUS_WIDTH (1U) 156 #define SBSW_TMC_CONFIG_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_CONFIG_STATUS_STATUS_SHIFT)) & SBSW_TMC_CONFIG_STATUS_STATUS_MASK) 157 /*! @} */ 158 159 /*! @name TMWDP_CONFIG_STATUS - TMWDP Configuration Status */ 160 /*! @{ */ 161 162 #define SBSW_TMWDP_CONFIG_STATUS_STATUS_MASK (0x1U) 163 #define SBSW_TMWDP_CONFIG_STATUS_STATUS_SHIFT (0U) 164 #define SBSW_TMWDP_CONFIG_STATUS_STATUS_WIDTH (1U) 165 #define SBSW_TMWDP_CONFIG_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_CONFIG_STATUS_STATUS_SHIFT)) & SBSW_TMWDP_CONFIG_STATUS_STATUS_MASK) 166 /*! @} */ 167 168 /*! @name DEBUG_MODE - Debug Mode */ 169 /*! @{ */ 170 171 #define SBSW_DEBUG_MODE_MODE_MASK (0x80000000U) 172 #define SBSW_DEBUG_MODE_MODE_SHIFT (31U) 173 #define SBSW_DEBUG_MODE_MODE_WIDTH (1U) 174 #define SBSW_DEBUG_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_DEBUG_MODE_MODE_SHIFT)) & SBSW_DEBUG_MODE_MODE_MASK) 175 /*! @} */ 176 177 /*! @name TMC_FAULT_STATUS - TMC Fault Status */ 178 /*! @{ */ 179 180 #define SBSW_TMC_FAULT_STATUS_STATUS0_MASK (0x1U) 181 #define SBSW_TMC_FAULT_STATUS_STATUS0_SHIFT (0U) 182 #define SBSW_TMC_FAULT_STATUS_STATUS0_WIDTH (1U) 183 #define SBSW_TMC_FAULT_STATUS_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS0_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS0_MASK) 184 185 #define SBSW_TMC_FAULT_STATUS_STATUS1_MASK (0x2U) 186 #define SBSW_TMC_FAULT_STATUS_STATUS1_SHIFT (1U) 187 #define SBSW_TMC_FAULT_STATUS_STATUS1_WIDTH (1U) 188 #define SBSW_TMC_FAULT_STATUS_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS1_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS1_MASK) 189 190 #define SBSW_TMC_FAULT_STATUS_STATUS2_MASK (0x4U) 191 #define SBSW_TMC_FAULT_STATUS_STATUS2_SHIFT (2U) 192 #define SBSW_TMC_FAULT_STATUS_STATUS2_WIDTH (1U) 193 #define SBSW_TMC_FAULT_STATUS_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS2_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS2_MASK) 194 195 #define SBSW_TMC_FAULT_STATUS_STATUS3_MASK (0x8U) 196 #define SBSW_TMC_FAULT_STATUS_STATUS3_SHIFT (3U) 197 #define SBSW_TMC_FAULT_STATUS_STATUS3_WIDTH (1U) 198 #define SBSW_TMC_FAULT_STATUS_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS3_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS3_MASK) 199 200 #define SBSW_TMC_FAULT_STATUS_STATUS4_MASK (0x10U) 201 #define SBSW_TMC_FAULT_STATUS_STATUS4_SHIFT (4U) 202 #define SBSW_TMC_FAULT_STATUS_STATUS4_WIDTH (1U) 203 #define SBSW_TMC_FAULT_STATUS_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS4_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS4_MASK) 204 205 #define SBSW_TMC_FAULT_STATUS_STATUS5_MASK (0x20U) 206 #define SBSW_TMC_FAULT_STATUS_STATUS5_SHIFT (5U) 207 #define SBSW_TMC_FAULT_STATUS_STATUS5_WIDTH (1U) 208 #define SBSW_TMC_FAULT_STATUS_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS5_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS5_MASK) 209 210 #define SBSW_TMC_FAULT_STATUS_STATUS6_MASK (0x40U) 211 #define SBSW_TMC_FAULT_STATUS_STATUS6_SHIFT (6U) 212 #define SBSW_TMC_FAULT_STATUS_STATUS6_WIDTH (1U) 213 #define SBSW_TMC_FAULT_STATUS_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS6_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS6_MASK) 214 215 #define SBSW_TMC_FAULT_STATUS_STATUS7_MASK (0x80U) 216 #define SBSW_TMC_FAULT_STATUS_STATUS7_SHIFT (7U) 217 #define SBSW_TMC_FAULT_STATUS_STATUS7_WIDTH (1U) 218 #define SBSW_TMC_FAULT_STATUS_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS7_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS7_MASK) 219 220 #define SBSW_TMC_FAULT_STATUS_STATUS8_MASK (0x100U) 221 #define SBSW_TMC_FAULT_STATUS_STATUS8_SHIFT (8U) 222 #define SBSW_TMC_FAULT_STATUS_STATUS8_WIDTH (1U) 223 #define SBSW_TMC_FAULT_STATUS_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS8_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS8_MASK) 224 225 #define SBSW_TMC_FAULT_STATUS_STATUS9_MASK (0x200U) 226 #define SBSW_TMC_FAULT_STATUS_STATUS9_SHIFT (9U) 227 #define SBSW_TMC_FAULT_STATUS_STATUS9_WIDTH (1U) 228 #define SBSW_TMC_FAULT_STATUS_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS9_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS9_MASK) 229 230 #define SBSW_TMC_FAULT_STATUS_STATUS10_MASK (0x400U) 231 #define SBSW_TMC_FAULT_STATUS_STATUS10_SHIFT (10U) 232 #define SBSW_TMC_FAULT_STATUS_STATUS10_WIDTH (1U) 233 #define SBSW_TMC_FAULT_STATUS_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS10_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS10_MASK) 234 235 #define SBSW_TMC_FAULT_STATUS_STATUS11_MASK (0x800U) 236 #define SBSW_TMC_FAULT_STATUS_STATUS11_SHIFT (11U) 237 #define SBSW_TMC_FAULT_STATUS_STATUS11_WIDTH (1U) 238 #define SBSW_TMC_FAULT_STATUS_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS11_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS11_MASK) 239 240 #define SBSW_TMC_FAULT_STATUS_STATUS12_MASK (0x1000U) 241 #define SBSW_TMC_FAULT_STATUS_STATUS12_SHIFT (12U) 242 #define SBSW_TMC_FAULT_STATUS_STATUS12_WIDTH (1U) 243 #define SBSW_TMC_FAULT_STATUS_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS12_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS12_MASK) 244 245 #define SBSW_TMC_FAULT_STATUS_STATUS13_MASK (0x2000U) 246 #define SBSW_TMC_FAULT_STATUS_STATUS13_SHIFT (13U) 247 #define SBSW_TMC_FAULT_STATUS_STATUS13_WIDTH (1U) 248 #define SBSW_TMC_FAULT_STATUS_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS13_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS13_MASK) 249 250 #define SBSW_TMC_FAULT_STATUS_STATUS14_MASK (0x4000U) 251 #define SBSW_TMC_FAULT_STATUS_STATUS14_SHIFT (14U) 252 #define SBSW_TMC_FAULT_STATUS_STATUS14_WIDTH (1U) 253 #define SBSW_TMC_FAULT_STATUS_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS14_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS14_MASK) 254 255 #define SBSW_TMC_FAULT_STATUS_STATUS15_MASK (0x8000U) 256 #define SBSW_TMC_FAULT_STATUS_STATUS15_SHIFT (15U) 257 #define SBSW_TMC_FAULT_STATUS_STATUS15_WIDTH (1U) 258 #define SBSW_TMC_FAULT_STATUS_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS15_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS15_MASK) 259 260 #define SBSW_TMC_FAULT_STATUS_STATUS16_MASK (0x10000U) 261 #define SBSW_TMC_FAULT_STATUS_STATUS16_SHIFT (16U) 262 #define SBSW_TMC_FAULT_STATUS_STATUS16_WIDTH (1U) 263 #define SBSW_TMC_FAULT_STATUS_STATUS16(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS16_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS16_MASK) 264 265 #define SBSW_TMC_FAULT_STATUS_STATUS17_MASK (0x20000U) 266 #define SBSW_TMC_FAULT_STATUS_STATUS17_SHIFT (17U) 267 #define SBSW_TMC_FAULT_STATUS_STATUS17_WIDTH (1U) 268 #define SBSW_TMC_FAULT_STATUS_STATUS17(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS17_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS17_MASK) 269 270 #define SBSW_TMC_FAULT_STATUS_STATUS18_MASK (0x40000U) 271 #define SBSW_TMC_FAULT_STATUS_STATUS18_SHIFT (18U) 272 #define SBSW_TMC_FAULT_STATUS_STATUS18_WIDTH (1U) 273 #define SBSW_TMC_FAULT_STATUS_STATUS18(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS18_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS18_MASK) 274 275 #define SBSW_TMC_FAULT_STATUS_STATUS19_MASK (0x80000U) 276 #define SBSW_TMC_FAULT_STATUS_STATUS19_SHIFT (19U) 277 #define SBSW_TMC_FAULT_STATUS_STATUS19_WIDTH (1U) 278 #define SBSW_TMC_FAULT_STATUS_STATUS19(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS19_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS19_MASK) 279 280 #define SBSW_TMC_FAULT_STATUS_STATUS20_MASK (0x100000U) 281 #define SBSW_TMC_FAULT_STATUS_STATUS20_SHIFT (20U) 282 #define SBSW_TMC_FAULT_STATUS_STATUS20_WIDTH (1U) 283 #define SBSW_TMC_FAULT_STATUS_STATUS20(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS20_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS20_MASK) 284 285 #define SBSW_TMC_FAULT_STATUS_STATUS21_MASK (0x200000U) 286 #define SBSW_TMC_FAULT_STATUS_STATUS21_SHIFT (21U) 287 #define SBSW_TMC_FAULT_STATUS_STATUS21_WIDTH (1U) 288 #define SBSW_TMC_FAULT_STATUS_STATUS21(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS21_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS21_MASK) 289 290 #define SBSW_TMC_FAULT_STATUS_STATUS22_MASK (0x400000U) 291 #define SBSW_TMC_FAULT_STATUS_STATUS22_SHIFT (22U) 292 #define SBSW_TMC_FAULT_STATUS_STATUS22_WIDTH (1U) 293 #define SBSW_TMC_FAULT_STATUS_STATUS22(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS22_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS22_MASK) 294 295 #define SBSW_TMC_FAULT_STATUS_STATUS23_MASK (0x800000U) 296 #define SBSW_TMC_FAULT_STATUS_STATUS23_SHIFT (23U) 297 #define SBSW_TMC_FAULT_STATUS_STATUS23_WIDTH (1U) 298 #define SBSW_TMC_FAULT_STATUS_STATUS23(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS23_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS23_MASK) 299 300 #define SBSW_TMC_FAULT_STATUS_STATUS24_MASK (0x1000000U) 301 #define SBSW_TMC_FAULT_STATUS_STATUS24_SHIFT (24U) 302 #define SBSW_TMC_FAULT_STATUS_STATUS24_WIDTH (1U) 303 #define SBSW_TMC_FAULT_STATUS_STATUS24(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS24_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS24_MASK) 304 305 #define SBSW_TMC_FAULT_STATUS_STATUS25_MASK (0x2000000U) 306 #define SBSW_TMC_FAULT_STATUS_STATUS25_SHIFT (25U) 307 #define SBSW_TMC_FAULT_STATUS_STATUS25_WIDTH (1U) 308 #define SBSW_TMC_FAULT_STATUS_STATUS25(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS25_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS25_MASK) 309 310 #define SBSW_TMC_FAULT_STATUS_STATUS26_MASK (0x4000000U) 311 #define SBSW_TMC_FAULT_STATUS_STATUS26_SHIFT (26U) 312 #define SBSW_TMC_FAULT_STATUS_STATUS26_WIDTH (1U) 313 #define SBSW_TMC_FAULT_STATUS_STATUS26(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS26_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS26_MASK) 314 315 #define SBSW_TMC_FAULT_STATUS_STATUS27_MASK (0x8000000U) 316 #define SBSW_TMC_FAULT_STATUS_STATUS27_SHIFT (27U) 317 #define SBSW_TMC_FAULT_STATUS_STATUS27_WIDTH (1U) 318 #define SBSW_TMC_FAULT_STATUS_STATUS27(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS27_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS27_MASK) 319 320 #define SBSW_TMC_FAULT_STATUS_STATUS28_MASK (0x10000000U) 321 #define SBSW_TMC_FAULT_STATUS_STATUS28_SHIFT (28U) 322 #define SBSW_TMC_FAULT_STATUS_STATUS28_WIDTH (1U) 323 #define SBSW_TMC_FAULT_STATUS_STATUS28(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS28_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS28_MASK) 324 325 #define SBSW_TMC_FAULT_STATUS_STATUS29_MASK (0x20000000U) 326 #define SBSW_TMC_FAULT_STATUS_STATUS29_SHIFT (29U) 327 #define SBSW_TMC_FAULT_STATUS_STATUS29_WIDTH (1U) 328 #define SBSW_TMC_FAULT_STATUS_STATUS29(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS29_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS29_MASK) 329 330 #define SBSW_TMC_FAULT_STATUS_STATUS30_MASK (0x40000000U) 331 #define SBSW_TMC_FAULT_STATUS_STATUS30_SHIFT (30U) 332 #define SBSW_TMC_FAULT_STATUS_STATUS30_WIDTH (1U) 333 #define SBSW_TMC_FAULT_STATUS_STATUS30(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS30_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS30_MASK) 334 335 #define SBSW_TMC_FAULT_STATUS_STATUS31_MASK (0x80000000U) 336 #define SBSW_TMC_FAULT_STATUS_STATUS31_SHIFT (31U) 337 #define SBSW_TMC_FAULT_STATUS_STATUS31_WIDTH (1U) 338 #define SBSW_TMC_FAULT_STATUS_STATUS31(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMC_FAULT_STATUS_STATUS31_SHIFT)) & SBSW_TMC_FAULT_STATUS_STATUS31_MASK) 339 /*! @} */ 340 341 /*! @name TMWDP_FAULT_STATUS - TMWDP Fault Status */ 342 /*! @{ */ 343 344 #define SBSW_TMWDP_FAULT_STATUS_STATUS0_MASK (0x1U) 345 #define SBSW_TMWDP_FAULT_STATUS_STATUS0_SHIFT (0U) 346 #define SBSW_TMWDP_FAULT_STATUS_STATUS0_WIDTH (1U) 347 #define SBSW_TMWDP_FAULT_STATUS_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS0_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS0_MASK) 348 349 #define SBSW_TMWDP_FAULT_STATUS_STATUS1_MASK (0x2U) 350 #define SBSW_TMWDP_FAULT_STATUS_STATUS1_SHIFT (1U) 351 #define SBSW_TMWDP_FAULT_STATUS_STATUS1_WIDTH (1U) 352 #define SBSW_TMWDP_FAULT_STATUS_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS1_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS1_MASK) 353 354 #define SBSW_TMWDP_FAULT_STATUS_STATUS2_MASK (0x4U) 355 #define SBSW_TMWDP_FAULT_STATUS_STATUS2_SHIFT (2U) 356 #define SBSW_TMWDP_FAULT_STATUS_STATUS2_WIDTH (1U) 357 #define SBSW_TMWDP_FAULT_STATUS_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS2_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS2_MASK) 358 359 #define SBSW_TMWDP_FAULT_STATUS_STATUS3_MASK (0x8U) 360 #define SBSW_TMWDP_FAULT_STATUS_STATUS3_SHIFT (3U) 361 #define SBSW_TMWDP_FAULT_STATUS_STATUS3_WIDTH (1U) 362 #define SBSW_TMWDP_FAULT_STATUS_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS3_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS3_MASK) 363 364 #define SBSW_TMWDP_FAULT_STATUS_STATUS4_MASK (0x10U) 365 #define SBSW_TMWDP_FAULT_STATUS_STATUS4_SHIFT (4U) 366 #define SBSW_TMWDP_FAULT_STATUS_STATUS4_WIDTH (1U) 367 #define SBSW_TMWDP_FAULT_STATUS_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS4_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS4_MASK) 368 369 #define SBSW_TMWDP_FAULT_STATUS_STATUS5_MASK (0x20U) 370 #define SBSW_TMWDP_FAULT_STATUS_STATUS5_SHIFT (5U) 371 #define SBSW_TMWDP_FAULT_STATUS_STATUS5_WIDTH (1U) 372 #define SBSW_TMWDP_FAULT_STATUS_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS5_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS5_MASK) 373 374 #define SBSW_TMWDP_FAULT_STATUS_STATUS6_MASK (0x40U) 375 #define SBSW_TMWDP_FAULT_STATUS_STATUS6_SHIFT (6U) 376 #define SBSW_TMWDP_FAULT_STATUS_STATUS6_WIDTH (1U) 377 #define SBSW_TMWDP_FAULT_STATUS_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS6_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS6_MASK) 378 379 #define SBSW_TMWDP_FAULT_STATUS_STATUS7_MASK (0x80U) 380 #define SBSW_TMWDP_FAULT_STATUS_STATUS7_SHIFT (7U) 381 #define SBSW_TMWDP_FAULT_STATUS_STATUS7_WIDTH (1U) 382 #define SBSW_TMWDP_FAULT_STATUS_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS7_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS7_MASK) 383 384 #define SBSW_TMWDP_FAULT_STATUS_STATUS8_MASK (0x100U) 385 #define SBSW_TMWDP_FAULT_STATUS_STATUS8_SHIFT (8U) 386 #define SBSW_TMWDP_FAULT_STATUS_STATUS8_WIDTH (1U) 387 #define SBSW_TMWDP_FAULT_STATUS_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS8_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS8_MASK) 388 389 #define SBSW_TMWDP_FAULT_STATUS_STATUS9_MASK (0x200U) 390 #define SBSW_TMWDP_FAULT_STATUS_STATUS9_SHIFT (9U) 391 #define SBSW_TMWDP_FAULT_STATUS_STATUS9_WIDTH (1U) 392 #define SBSW_TMWDP_FAULT_STATUS_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS9_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS9_MASK) 393 394 #define SBSW_TMWDP_FAULT_STATUS_STATUS10_MASK (0x400U) 395 #define SBSW_TMWDP_FAULT_STATUS_STATUS10_SHIFT (10U) 396 #define SBSW_TMWDP_FAULT_STATUS_STATUS10_WIDTH (1U) 397 #define SBSW_TMWDP_FAULT_STATUS_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS10_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS10_MASK) 398 399 #define SBSW_TMWDP_FAULT_STATUS_STATUS11_MASK (0x800U) 400 #define SBSW_TMWDP_FAULT_STATUS_STATUS11_SHIFT (11U) 401 #define SBSW_TMWDP_FAULT_STATUS_STATUS11_WIDTH (1U) 402 #define SBSW_TMWDP_FAULT_STATUS_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS11_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS11_MASK) 403 404 #define SBSW_TMWDP_FAULT_STATUS_STATUS12_MASK (0x1000U) 405 #define SBSW_TMWDP_FAULT_STATUS_STATUS12_SHIFT (12U) 406 #define SBSW_TMWDP_FAULT_STATUS_STATUS12_WIDTH (1U) 407 #define SBSW_TMWDP_FAULT_STATUS_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS12_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS12_MASK) 408 409 #define SBSW_TMWDP_FAULT_STATUS_STATUS13_MASK (0x2000U) 410 #define SBSW_TMWDP_FAULT_STATUS_STATUS13_SHIFT (13U) 411 #define SBSW_TMWDP_FAULT_STATUS_STATUS13_WIDTH (1U) 412 #define SBSW_TMWDP_FAULT_STATUS_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS13_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS13_MASK) 413 414 #define SBSW_TMWDP_FAULT_STATUS_STATUS14_MASK (0x4000U) 415 #define SBSW_TMWDP_FAULT_STATUS_STATUS14_SHIFT (14U) 416 #define SBSW_TMWDP_FAULT_STATUS_STATUS14_WIDTH (1U) 417 #define SBSW_TMWDP_FAULT_STATUS_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS14_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS14_MASK) 418 419 #define SBSW_TMWDP_FAULT_STATUS_STATUS15_MASK (0x8000U) 420 #define SBSW_TMWDP_FAULT_STATUS_STATUS15_SHIFT (15U) 421 #define SBSW_TMWDP_FAULT_STATUS_STATUS15_WIDTH (1U) 422 #define SBSW_TMWDP_FAULT_STATUS_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS15_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS15_MASK) 423 424 #define SBSW_TMWDP_FAULT_STATUS_STATUS16_MASK (0x10000U) 425 #define SBSW_TMWDP_FAULT_STATUS_STATUS16_SHIFT (16U) 426 #define SBSW_TMWDP_FAULT_STATUS_STATUS16_WIDTH (1U) 427 #define SBSW_TMWDP_FAULT_STATUS_STATUS16(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS16_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS16_MASK) 428 429 #define SBSW_TMWDP_FAULT_STATUS_STATUS17_MASK (0x20000U) 430 #define SBSW_TMWDP_FAULT_STATUS_STATUS17_SHIFT (17U) 431 #define SBSW_TMWDP_FAULT_STATUS_STATUS17_WIDTH (1U) 432 #define SBSW_TMWDP_FAULT_STATUS_STATUS17(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS17_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS17_MASK) 433 434 #define SBSW_TMWDP_FAULT_STATUS_STATUS18_MASK (0x40000U) 435 #define SBSW_TMWDP_FAULT_STATUS_STATUS18_SHIFT (18U) 436 #define SBSW_TMWDP_FAULT_STATUS_STATUS18_WIDTH (1U) 437 #define SBSW_TMWDP_FAULT_STATUS_STATUS18(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS18_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS18_MASK) 438 439 #define SBSW_TMWDP_FAULT_STATUS_STATUS19_MASK (0x80000U) 440 #define SBSW_TMWDP_FAULT_STATUS_STATUS19_SHIFT (19U) 441 #define SBSW_TMWDP_FAULT_STATUS_STATUS19_WIDTH (1U) 442 #define SBSW_TMWDP_FAULT_STATUS_STATUS19(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS19_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS19_MASK) 443 444 #define SBSW_TMWDP_FAULT_STATUS_STATUS20_MASK (0x100000U) 445 #define SBSW_TMWDP_FAULT_STATUS_STATUS20_SHIFT (20U) 446 #define SBSW_TMWDP_FAULT_STATUS_STATUS20_WIDTH (1U) 447 #define SBSW_TMWDP_FAULT_STATUS_STATUS20(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS20_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS20_MASK) 448 449 #define SBSW_TMWDP_FAULT_STATUS_STATUS21_MASK (0x200000U) 450 #define SBSW_TMWDP_FAULT_STATUS_STATUS21_SHIFT (21U) 451 #define SBSW_TMWDP_FAULT_STATUS_STATUS21_WIDTH (1U) 452 #define SBSW_TMWDP_FAULT_STATUS_STATUS21(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS21_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS21_MASK) 453 454 #define SBSW_TMWDP_FAULT_STATUS_STATUS22_MASK (0x400000U) 455 #define SBSW_TMWDP_FAULT_STATUS_STATUS22_SHIFT (22U) 456 #define SBSW_TMWDP_FAULT_STATUS_STATUS22_WIDTH (1U) 457 #define SBSW_TMWDP_FAULT_STATUS_STATUS22(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS22_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS22_MASK) 458 459 #define SBSW_TMWDP_FAULT_STATUS_STATUS23_MASK (0x800000U) 460 #define SBSW_TMWDP_FAULT_STATUS_STATUS23_SHIFT (23U) 461 #define SBSW_TMWDP_FAULT_STATUS_STATUS23_WIDTH (1U) 462 #define SBSW_TMWDP_FAULT_STATUS_STATUS23(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS23_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS23_MASK) 463 464 #define SBSW_TMWDP_FAULT_STATUS_STATUS24_MASK (0x1000000U) 465 #define SBSW_TMWDP_FAULT_STATUS_STATUS24_SHIFT (24U) 466 #define SBSW_TMWDP_FAULT_STATUS_STATUS24_WIDTH (1U) 467 #define SBSW_TMWDP_FAULT_STATUS_STATUS24(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS24_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS24_MASK) 468 469 #define SBSW_TMWDP_FAULT_STATUS_STATUS25_MASK (0x2000000U) 470 #define SBSW_TMWDP_FAULT_STATUS_STATUS25_SHIFT (25U) 471 #define SBSW_TMWDP_FAULT_STATUS_STATUS25_WIDTH (1U) 472 #define SBSW_TMWDP_FAULT_STATUS_STATUS25(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS25_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS25_MASK) 473 474 #define SBSW_TMWDP_FAULT_STATUS_STATUS26_MASK (0x4000000U) 475 #define SBSW_TMWDP_FAULT_STATUS_STATUS26_SHIFT (26U) 476 #define SBSW_TMWDP_FAULT_STATUS_STATUS26_WIDTH (1U) 477 #define SBSW_TMWDP_FAULT_STATUS_STATUS26(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS26_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS26_MASK) 478 479 #define SBSW_TMWDP_FAULT_STATUS_STATUS27_MASK (0x8000000U) 480 #define SBSW_TMWDP_FAULT_STATUS_STATUS27_SHIFT (27U) 481 #define SBSW_TMWDP_FAULT_STATUS_STATUS27_WIDTH (1U) 482 #define SBSW_TMWDP_FAULT_STATUS_STATUS27(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS27_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS27_MASK) 483 484 #define SBSW_TMWDP_FAULT_STATUS_STATUS28_MASK (0x10000000U) 485 #define SBSW_TMWDP_FAULT_STATUS_STATUS28_SHIFT (28U) 486 #define SBSW_TMWDP_FAULT_STATUS_STATUS28_WIDTH (1U) 487 #define SBSW_TMWDP_FAULT_STATUS_STATUS28(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS28_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS28_MASK) 488 489 #define SBSW_TMWDP_FAULT_STATUS_STATUS29_MASK (0x20000000U) 490 #define SBSW_TMWDP_FAULT_STATUS_STATUS29_SHIFT (29U) 491 #define SBSW_TMWDP_FAULT_STATUS_STATUS29_WIDTH (1U) 492 #define SBSW_TMWDP_FAULT_STATUS_STATUS29(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS29_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS29_MASK) 493 494 #define SBSW_TMWDP_FAULT_STATUS_STATUS30_MASK (0x40000000U) 495 #define SBSW_TMWDP_FAULT_STATUS_STATUS30_SHIFT (30U) 496 #define SBSW_TMWDP_FAULT_STATUS_STATUS30_WIDTH (1U) 497 #define SBSW_TMWDP_FAULT_STATUS_STATUS30(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS30_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS30_MASK) 498 499 #define SBSW_TMWDP_FAULT_STATUS_STATUS31_MASK (0x80000000U) 500 #define SBSW_TMWDP_FAULT_STATUS_STATUS31_SHIFT (31U) 501 #define SBSW_TMWDP_FAULT_STATUS_STATUS31_WIDTH (1U) 502 #define SBSW_TMWDP_FAULT_STATUS_STATUS31(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_FAULT_STATUS_STATUS31_SHIFT)) & SBSW_TMWDP_FAULT_STATUS_STATUS31_MASK) 503 /*! @} */ 504 505 /*! @name CONFIG - TMC Configuration */ 506 /*! @{ */ 507 508 #define SBSW_CONFIG_TIMING_MODE_MASK (0x1U) 509 #define SBSW_CONFIG_TIMING_MODE_SHIFT (0U) 510 #define SBSW_CONFIG_TIMING_MODE_WIDTH (1U) 511 #define SBSW_CONFIG_TIMING_MODE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_CONFIG_TIMING_MODE_SHIFT)) & SBSW_CONFIG_TIMING_MODE_MASK) 512 513 #define SBSW_CONFIG_COMPARE_MODE_MASK (0x6U) 514 #define SBSW_CONFIG_COMPARE_MODE_SHIFT (1U) 515 #define SBSW_CONFIG_COMPARE_MODE_WIDTH (2U) 516 #define SBSW_CONFIG_COMPARE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_CONFIG_COMPARE_MODE_SHIFT)) & SBSW_CONFIG_COMPARE_MODE_MASK) 517 /*! @} */ 518 519 /*! @name DISTANCE - TMC Distance */ 520 /*! @{ */ 521 522 #define SBSW_DISTANCE_DISTANCE_MASK (0xFFFFFFFFU) 523 #define SBSW_DISTANCE_DISTANCE_SHIFT (0U) 524 #define SBSW_DISTANCE_DISTANCE_WIDTH (32U) 525 #define SBSW_DISTANCE_DISTANCE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_DISTANCE_DISTANCE_SHIFT)) & SBSW_DISTANCE_DISTANCE_MASK) 526 /*! @} */ 527 528 /*! @name TIMEOUT - TMC Timeout */ 529 /*! @{ */ 530 531 #define SBSW_TIMEOUT_TIMEOUT_MASK (0xFFFFFFFFU) 532 #define SBSW_TIMEOUT_TIMEOUT_SHIFT (0U) 533 #define SBSW_TIMEOUT_TIMEOUT_WIDTH (32U) 534 #define SBSW_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TIMEOUT_TIMEOUT_SHIFT)) & SBSW_TIMEOUT_TIMEOUT_MASK) 535 /*! @} */ 536 537 /*! @name CONTROL - TMC Control */ 538 /*! @{ */ 539 540 #define SBSW_CONTROL_ENABLE_MASK (0x1U) 541 #define SBSW_CONTROL_ENABLE_SHIFT (0U) 542 #define SBSW_CONTROL_ENABLE_WIDTH (1U) 543 #define SBSW_CONTROL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_CONTROL_ENABLE_SHIFT)) & SBSW_CONTROL_ENABLE_MASK) 544 /*! @} */ 545 546 /*! @name R0 - TMC R0 Data */ 547 /*! @{ */ 548 549 #define SBSW_R0_R0_MASK (0xFFFFFFFFU) 550 #define SBSW_R0_R0_SHIFT (0U) 551 #define SBSW_R0_R0_WIDTH (32U) 552 #define SBSW_R0_R0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_R0_R0_SHIFT)) & SBSW_R0_R0_MASK) 553 /*! @} */ 554 555 /*! @name R1 - TMC R1 Data */ 556 /*! @{ */ 557 558 #define SBSW_R1_R1_MASK (0xFFFFFFFFU) 559 #define SBSW_R1_R1_SHIFT (0U) 560 #define SBSW_R1_R1_WIDTH (32U) 561 #define SBSW_R1_R1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_R1_R1_SHIFT)) & SBSW_R1_R1_MASK) 562 /*! @} */ 563 564 /*! @name STATUS - TMC Status */ 565 /*! @{ */ 566 567 #define SBSW_STATUS_R0_WRITTEN_MASK (0x1U) 568 #define SBSW_STATUS_R0_WRITTEN_SHIFT (0U) 569 #define SBSW_STATUS_R0_WRITTEN_WIDTH (1U) 570 #define SBSW_STATUS_R0_WRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_R0_WRITTEN_SHIFT)) & SBSW_STATUS_R0_WRITTEN_MASK) 571 572 #define SBSW_STATUS_R1_WRITTEN_MASK (0x2U) 573 #define SBSW_STATUS_R1_WRITTEN_SHIFT (1U) 574 #define SBSW_STATUS_R1_WRITTEN_WIDTH (1U) 575 #define SBSW_STATUS_R1_WRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_R1_WRITTEN_SHIFT)) & SBSW_STATUS_R1_WRITTEN_MASK) 576 577 #define SBSW_STATUS_FAULT_MASK (0xCU) 578 #define SBSW_STATUS_FAULT_SHIFT (2U) 579 #define SBSW_STATUS_FAULT_WIDTH (2U) 580 #define SBSW_STATUS_FAULT(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_FAULT_SHIFT)) & SBSW_STATUS_FAULT_MASK) 581 582 #define SBSW_STATUS_OVERWRITTEN_MASK (0x10U) 583 #define SBSW_STATUS_OVERWRITTEN_SHIFT (4U) 584 #define SBSW_STATUS_OVERWRITTEN_WIDTH (1U) 585 #define SBSW_STATUS_OVERWRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_OVERWRITTEN_SHIFT)) & SBSW_STATUS_OVERWRITTEN_MASK) 586 /*! @} */ 587 588 /*! @name TIMER - TMC Timer */ 589 /*! @{ */ 590 591 #define SBSW_TIMER_TIMER_MASK (0xFFFFFFFFU) 592 #define SBSW_TIMER_TIMER_SHIFT (0U) 593 #define SBSW_TIMER_TIMER_WIDTH (32U) 594 #define SBSW_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TIMER_TIMER_SHIFT)) & SBSW_TIMER_TIMER_MASK) 595 /*! @} */ 596 597 /*! @name TMWDP_CONFIG_ADDR - TMWDP Configuration Address */ 598 /*! @{ */ 599 600 #define SBSW_TMWDP_CONFIG_ADDR_ADDRESS_MASK (0xFFFFFFFFU) 601 #define SBSW_TMWDP_CONFIG_ADDR_ADDRESS_SHIFT (0U) 602 #define SBSW_TMWDP_CONFIG_ADDR_ADDRESS_WIDTH (32U) 603 #define SBSW_TMWDP_CONFIG_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_CONFIG_ADDR_ADDRESS_SHIFT)) & SBSW_TMWDP_CONFIG_ADDR_ADDRESS_MASK) 604 /*! @} */ 605 606 /*! @name TMWDP_CONTROL - TMWDP Control */ 607 /*! @{ */ 608 609 #define SBSW_TMWDP_CONTROL_ENABLE_MASK (0x1U) 610 #define SBSW_TMWDP_CONTROL_ENABLE_SHIFT (0U) 611 #define SBSW_TMWDP_CONTROL_ENABLE_WIDTH (1U) 612 #define SBSW_TMWDP_CONTROL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_CONTROL_ENABLE_SHIFT)) & SBSW_TMWDP_CONTROL_ENABLE_MASK) 613 /*! @} */ 614 615 /*! @name TMWDP_STATUS - TMWDP Status */ 616 /*! @{ */ 617 618 #define SBSW_TMWDP_STATUS_INTERNAL_ERROR_MASK (0x1U) 619 #define SBSW_TMWDP_STATUS_INTERNAL_ERROR_SHIFT (0U) 620 #define SBSW_TMWDP_STATUS_INTERNAL_ERROR_WIDTH (1U) 621 #define SBSW_TMWDP_STATUS_INTERNAL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_STATUS_INTERNAL_ERROR_SHIFT)) & SBSW_TMWDP_STATUS_INTERNAL_ERROR_MASK) 622 623 #define SBSW_TMWDP_STATUS_CONFIG_ERROR_MASK (0x2U) 624 #define SBSW_TMWDP_STATUS_CONFIG_ERROR_SHIFT (1U) 625 #define SBSW_TMWDP_STATUS_CONFIG_ERROR_WIDTH (1U) 626 #define SBSW_TMWDP_STATUS_CONFIG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_STATUS_CONFIG_ERROR_SHIFT)) & SBSW_TMWDP_STATUS_CONFIG_ERROR_MASK) 627 628 #define SBSW_TMWDP_STATUS_RUNNING_MASK (0x4U) 629 #define SBSW_TMWDP_STATUS_RUNNING_SHIFT (2U) 630 #define SBSW_TMWDP_STATUS_RUNNING_WIDTH (1U) 631 #define SBSW_TMWDP_STATUS_RUNNING(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_STATUS_RUNNING_SHIFT)) & SBSW_TMWDP_STATUS_RUNNING_MASK) 632 /*! @} */ 633 634 /*! @name TMWDP_AUTOMATA_STATUS - TMWDP Automata Status */ 635 /*! @{ */ 636 637 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS0_MASK (0x1U) 638 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS0_SHIFT (0U) 639 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS0_WIDTH (1U) 640 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS0_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS0_MASK) 641 642 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS1_MASK (0x2U) 643 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS1_SHIFT (1U) 644 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS1_WIDTH (1U) 645 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS1_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS1_MASK) 646 647 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS2_MASK (0x4U) 648 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS2_SHIFT (2U) 649 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS2_WIDTH (1U) 650 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS2_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS2_MASK) 651 652 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS3_MASK (0x8U) 653 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS3_SHIFT (3U) 654 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS3_WIDTH (1U) 655 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS3_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS3_MASK) 656 657 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS4_MASK (0x10U) 658 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS4_SHIFT (4U) 659 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS4_WIDTH (1U) 660 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS4_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS4_MASK) 661 662 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS5_MASK (0x20U) 663 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS5_SHIFT (5U) 664 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS5_WIDTH (1U) 665 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS5_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS5_MASK) 666 667 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS6_MASK (0x40U) 668 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS6_SHIFT (6U) 669 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS6_WIDTH (1U) 670 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS6_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS6_MASK) 671 672 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS7_MASK (0x80U) 673 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS7_SHIFT (7U) 674 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS7_WIDTH (1U) 675 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS7_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS7_MASK) 676 677 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS8_MASK (0x100U) 678 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS8_SHIFT (8U) 679 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS8_WIDTH (1U) 680 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS8_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS8_MASK) 681 682 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS9_MASK (0x200U) 683 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS9_SHIFT (9U) 684 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS9_WIDTH (1U) 685 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS9_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS9_MASK) 686 687 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS10_MASK (0x400U) 688 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS10_SHIFT (10U) 689 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS10_WIDTH (1U) 690 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS10_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS10_MASK) 691 692 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS11_MASK (0x800U) 693 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS11_SHIFT (11U) 694 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS11_WIDTH (1U) 695 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS11_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS11_MASK) 696 697 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS12_MASK (0x1000U) 698 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS12_SHIFT (12U) 699 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS12_WIDTH (1U) 700 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS12_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS12_MASK) 701 702 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS13_MASK (0x2000U) 703 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS13_SHIFT (13U) 704 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS13_WIDTH (1U) 705 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS13_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS13_MASK) 706 707 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS14_MASK (0x4000U) 708 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS14_SHIFT (14U) 709 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS14_WIDTH (1U) 710 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS14_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS14_MASK) 711 712 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS15_MASK (0x8000U) 713 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS15_SHIFT (15U) 714 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS15_WIDTH (1U) 715 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS15_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS15_MASK) 716 717 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS16_MASK (0x10000U) 718 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS16_SHIFT (16U) 719 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS16_WIDTH (1U) 720 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS16(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS16_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS16_MASK) 721 722 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS17_MASK (0x20000U) 723 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS17_SHIFT (17U) 724 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS17_WIDTH (1U) 725 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS17(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS17_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS17_MASK) 726 727 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS18_MASK (0x40000U) 728 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS18_SHIFT (18U) 729 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS18_WIDTH (1U) 730 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS18(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS18_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS18_MASK) 731 732 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS19_MASK (0x80000U) 733 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS19_SHIFT (19U) 734 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS19_WIDTH (1U) 735 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS19(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS19_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS19_MASK) 736 737 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS20_MASK (0x100000U) 738 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS20_SHIFT (20U) 739 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS20_WIDTH (1U) 740 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS20(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS20_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS20_MASK) 741 742 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS21_MASK (0x200000U) 743 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS21_SHIFT (21U) 744 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS21_WIDTH (1U) 745 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS21(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS21_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS21_MASK) 746 747 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS22_MASK (0x400000U) 748 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS22_SHIFT (22U) 749 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS22_WIDTH (1U) 750 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS22(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS22_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS22_MASK) 751 752 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS23_MASK (0x800000U) 753 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS23_SHIFT (23U) 754 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS23_WIDTH (1U) 755 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS23(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS23_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS23_MASK) 756 757 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS24_MASK (0x1000000U) 758 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS24_SHIFT (24U) 759 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS24_WIDTH (1U) 760 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS24(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS24_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS24_MASK) 761 762 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS25_MASK (0x2000000U) 763 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS25_SHIFT (25U) 764 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS25_WIDTH (1U) 765 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS25(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS25_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS25_MASK) 766 767 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS26_MASK (0x4000000U) 768 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS26_SHIFT (26U) 769 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS26_WIDTH (1U) 770 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS26(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS26_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS26_MASK) 771 772 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS27_MASK (0x8000000U) 773 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS27_SHIFT (27U) 774 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS27_WIDTH (1U) 775 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS27(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS27_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS27_MASK) 776 777 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS28_MASK (0x10000000U) 778 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS28_SHIFT (28U) 779 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS28_WIDTH (1U) 780 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS28(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS28_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS28_MASK) 781 782 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS29_MASK (0x20000000U) 783 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS29_SHIFT (29U) 784 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS29_WIDTH (1U) 785 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS29(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS29_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS29_MASK) 786 787 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS30_MASK (0x40000000U) 788 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS30_SHIFT (30U) 789 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS30_WIDTH (1U) 790 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS30(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS30_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS30_MASK) 791 792 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS31_MASK (0x80000000U) 793 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS31_SHIFT (31U) 794 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS31_WIDTH (1U) 795 #define SBSW_TMWDP_AUTOMATA_STATUS_STATUS31(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_STATUS_STATUS31_SHIFT)) & SBSW_TMWDP_AUTOMATA_STATUS_STATUS31_MASK) 796 /*! @} */ 797 798 /*! @name TMWDP_AUTOMATA_ILLGL_TRANS - TMWDP Automata Illegal Transition */ 799 /*! @{ */ 800 801 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0_MASK (0x1U) 802 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0_SHIFT (0U) 803 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0_WIDTH (1U) 804 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS0_MASK) 805 806 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1_MASK (0x2U) 807 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1_SHIFT (1U) 808 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1_WIDTH (1U) 809 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS1_MASK) 810 811 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2_MASK (0x4U) 812 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2_SHIFT (2U) 813 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2_WIDTH (1U) 814 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS2_MASK) 815 816 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3_MASK (0x8U) 817 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3_SHIFT (3U) 818 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3_WIDTH (1U) 819 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS3_MASK) 820 821 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4_MASK (0x10U) 822 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4_SHIFT (4U) 823 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4_WIDTH (1U) 824 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS4_MASK) 825 826 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5_MASK (0x20U) 827 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5_SHIFT (5U) 828 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5_WIDTH (1U) 829 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS5_MASK) 830 831 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6_MASK (0x40U) 832 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6_SHIFT (6U) 833 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6_WIDTH (1U) 834 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS6_MASK) 835 836 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7_MASK (0x80U) 837 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7_SHIFT (7U) 838 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7_WIDTH (1U) 839 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS7_MASK) 840 841 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8_MASK (0x100U) 842 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8_SHIFT (8U) 843 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8_WIDTH (1U) 844 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS8_MASK) 845 846 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9_MASK (0x200U) 847 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9_SHIFT (9U) 848 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9_WIDTH (1U) 849 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS9_MASK) 850 851 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10_MASK (0x400U) 852 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10_SHIFT (10U) 853 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10_WIDTH (1U) 854 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS10_MASK) 855 856 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11_MASK (0x800U) 857 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11_SHIFT (11U) 858 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11_WIDTH (1U) 859 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS11_MASK) 860 861 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12_MASK (0x1000U) 862 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12_SHIFT (12U) 863 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12_WIDTH (1U) 864 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS12_MASK) 865 866 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13_MASK (0x2000U) 867 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13_SHIFT (13U) 868 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13_WIDTH (1U) 869 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS13_MASK) 870 871 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14_MASK (0x4000U) 872 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14_SHIFT (14U) 873 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14_WIDTH (1U) 874 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS14_MASK) 875 876 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15_MASK (0x8000U) 877 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15_SHIFT (15U) 878 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15_WIDTH (1U) 879 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS15_MASK) 880 881 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16_MASK (0x10000U) 882 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16_SHIFT (16U) 883 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16_WIDTH (1U) 884 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS16_MASK) 885 886 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17_MASK (0x20000U) 887 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17_SHIFT (17U) 888 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17_WIDTH (1U) 889 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS17_MASK) 890 891 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18_MASK (0x40000U) 892 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18_SHIFT (18U) 893 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18_WIDTH (1U) 894 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS18_MASK) 895 896 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19_MASK (0x80000U) 897 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19_SHIFT (19U) 898 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19_WIDTH (1U) 899 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS19_MASK) 900 901 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20_MASK (0x100000U) 902 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20_SHIFT (20U) 903 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20_WIDTH (1U) 904 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS20_MASK) 905 906 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21_MASK (0x200000U) 907 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21_SHIFT (21U) 908 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21_WIDTH (1U) 909 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS21_MASK) 910 911 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22_MASK (0x400000U) 912 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22_SHIFT (22U) 913 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22_WIDTH (1U) 914 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS22_MASK) 915 916 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23_MASK (0x800000U) 917 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23_SHIFT (23U) 918 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23_WIDTH (1U) 919 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS23_MASK) 920 921 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24_MASK (0x1000000U) 922 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24_SHIFT (24U) 923 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24_WIDTH (1U) 924 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS24_MASK) 925 926 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25_MASK (0x2000000U) 927 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25_SHIFT (25U) 928 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25_WIDTH (1U) 929 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS25_MASK) 930 931 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26_MASK (0x4000000U) 932 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26_SHIFT (26U) 933 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26_WIDTH (1U) 934 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS26_MASK) 935 936 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27_MASK (0x8000000U) 937 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27_SHIFT (27U) 938 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27_WIDTH (1U) 939 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS27_MASK) 940 941 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28_MASK (0x10000000U) 942 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28_SHIFT (28U) 943 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28_WIDTH (1U) 944 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS28_MASK) 945 946 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29_MASK (0x20000000U) 947 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29_SHIFT (29U) 948 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29_WIDTH (1U) 949 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS29_MASK) 950 951 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30_MASK (0x40000000U) 952 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30_SHIFT (30U) 953 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30_WIDTH (1U) 954 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS30_MASK) 955 956 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31_MASK (0x80000000U) 957 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31_SHIFT (31U) 958 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31_WIDTH (1U) 959 #define SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31_SHIFT)) & SBSW_TMWDP_AUTOMATA_ILLGL_TRANS_STATUS31_MASK) 960 /*! @} */ 961 962 /*! @name TMWDP_AUTOMATA_TIME_VIOLATION - TMWDP Automata Time Violation */ 963 /*! @{ */ 964 965 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0_MASK (0x1U) 966 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0_SHIFT (0U) 967 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0_WIDTH (1U) 968 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS0_MASK) 969 970 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1_MASK (0x2U) 971 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1_SHIFT (1U) 972 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1_WIDTH (1U) 973 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS1_MASK) 974 975 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2_MASK (0x4U) 976 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2_SHIFT (2U) 977 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2_WIDTH (1U) 978 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS2_MASK) 979 980 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3_MASK (0x8U) 981 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3_SHIFT (3U) 982 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3_WIDTH (1U) 983 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS3_MASK) 984 985 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4_MASK (0x10U) 986 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4_SHIFT (4U) 987 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4_WIDTH (1U) 988 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS4_MASK) 989 990 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5_MASK (0x20U) 991 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5_SHIFT (5U) 992 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5_WIDTH (1U) 993 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS5_MASK) 994 995 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6_MASK (0x40U) 996 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6_SHIFT (6U) 997 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6_WIDTH (1U) 998 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS6_MASK) 999 1000 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7_MASK (0x80U) 1001 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7_SHIFT (7U) 1002 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7_WIDTH (1U) 1003 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS7_MASK) 1004 1005 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8_MASK (0x100U) 1006 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8_SHIFT (8U) 1007 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8_WIDTH (1U) 1008 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS8_MASK) 1009 1010 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9_MASK (0x200U) 1011 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9_SHIFT (9U) 1012 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9_WIDTH (1U) 1013 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS9_MASK) 1014 1015 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10_MASK (0x400U) 1016 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10_SHIFT (10U) 1017 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10_WIDTH (1U) 1018 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS10_MASK) 1019 1020 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11_MASK (0x800U) 1021 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11_SHIFT (11U) 1022 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11_WIDTH (1U) 1023 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS11_MASK) 1024 1025 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12_MASK (0x1000U) 1026 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12_SHIFT (12U) 1027 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12_WIDTH (1U) 1028 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS12_MASK) 1029 1030 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13_MASK (0x2000U) 1031 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13_SHIFT (13U) 1032 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13_WIDTH (1U) 1033 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS13_MASK) 1034 1035 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14_MASK (0x4000U) 1036 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14_SHIFT (14U) 1037 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14_WIDTH (1U) 1038 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS14_MASK) 1039 1040 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15_MASK (0x8000U) 1041 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15_SHIFT (15U) 1042 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15_WIDTH (1U) 1043 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS15_MASK) 1044 1045 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16_MASK (0x10000U) 1046 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16_SHIFT (16U) 1047 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16_WIDTH (1U) 1048 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS16_MASK) 1049 1050 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17_MASK (0x20000U) 1051 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17_SHIFT (17U) 1052 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17_WIDTH (1U) 1053 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS17_MASK) 1054 1055 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18_MASK (0x40000U) 1056 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18_SHIFT (18U) 1057 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18_WIDTH (1U) 1058 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS18_MASK) 1059 1060 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19_MASK (0x80000U) 1061 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19_SHIFT (19U) 1062 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19_WIDTH (1U) 1063 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS19_MASK) 1064 1065 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20_MASK (0x100000U) 1066 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20_SHIFT (20U) 1067 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20_WIDTH (1U) 1068 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS20_MASK) 1069 1070 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21_MASK (0x200000U) 1071 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21_SHIFT (21U) 1072 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21_WIDTH (1U) 1073 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS21_MASK) 1074 1075 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22_MASK (0x400000U) 1076 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22_SHIFT (22U) 1077 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22_WIDTH (1U) 1078 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS22_MASK) 1079 1080 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23_MASK (0x800000U) 1081 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23_SHIFT (23U) 1082 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23_WIDTH (1U) 1083 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS23_MASK) 1084 1085 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24_MASK (0x1000000U) 1086 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24_SHIFT (24U) 1087 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24_WIDTH (1U) 1088 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS24_MASK) 1089 1090 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25_MASK (0x2000000U) 1091 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25_SHIFT (25U) 1092 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25_WIDTH (1U) 1093 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS25_MASK) 1094 1095 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26_MASK (0x4000000U) 1096 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26_SHIFT (26U) 1097 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26_WIDTH (1U) 1098 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS26_MASK) 1099 1100 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27_MASK (0x8000000U) 1101 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27_SHIFT (27U) 1102 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27_WIDTH (1U) 1103 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS27_MASK) 1104 1105 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28_MASK (0x10000000U) 1106 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28_SHIFT (28U) 1107 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28_WIDTH (1U) 1108 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS28_MASK) 1109 1110 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29_MASK (0x20000000U) 1111 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29_SHIFT (29U) 1112 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29_WIDTH (1U) 1113 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS29_MASK) 1114 1115 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30_MASK (0x40000000U) 1116 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30_SHIFT (30U) 1117 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30_WIDTH (1U) 1118 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS30_MASK) 1119 1120 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31_MASK (0x80000000U) 1121 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31_SHIFT (31U) 1122 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31_WIDTH (1U) 1123 #define SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31_SHIFT)) & SBSW_TMWDP_AUTOMATA_TIME_VIOLATION_STATUS31_MASK) 1124 /*! @} */ 1125 1126 /*! @name STATUS - TMWDP Automaton Status */ 1127 /*! @{ */ 1128 1129 #define SBSW_STATUS_CURRENT_STATE_MASK (0xFFFFU) 1130 #define SBSW_STATUS_CURRENT_STATE_SHIFT (0U) 1131 #define SBSW_STATUS_CURRENT_STATE_WIDTH (16U) 1132 #define SBSW_STATUS_CURRENT_STATE(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_CURRENT_STATE_SHIFT)) & SBSW_STATUS_CURRENT_STATE_MASK) 1133 1134 #define SBSW_STATUS_STATUS_MASK (0x10000U) 1135 #define SBSW_STATUS_STATUS_SHIFT (16U) 1136 #define SBSW_STATUS_STATUS_WIDTH (1U) 1137 #define SBSW_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_STATUS_SHIFT)) & SBSW_STATUS_STATUS_MASK) 1138 1139 #define SBSW_STATUS_ILLEGAL_TRANSITION_MASK (0x20000U) 1140 #define SBSW_STATUS_ILLEGAL_TRANSITION_SHIFT (17U) 1141 #define SBSW_STATUS_ILLEGAL_TRANSITION_WIDTH (1U) 1142 #define SBSW_STATUS_ILLEGAL_TRANSITION(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_ILLEGAL_TRANSITION_SHIFT)) & SBSW_STATUS_ILLEGAL_TRANSITION_MASK) 1143 1144 #define SBSW_STATUS_TIME_VIOLATION_MASK (0x40000U) 1145 #define SBSW_STATUS_TIME_VIOLATION_SHIFT (18U) 1146 #define SBSW_STATUS_TIME_VIOLATION_WIDTH (1U) 1147 #define SBSW_STATUS_TIME_VIOLATION(x) (((uint32_t)(((uint32_t)(x)) << SBSW_STATUS_TIME_VIOLATION_SHIFT)) & SBSW_STATUS_TIME_VIOLATION_MASK) 1148 /*! @} */ 1149 1150 /*! @name PRGS_REQ - TMWDP Automaton Progress Request */ 1151 /*! @{ */ 1152 1153 #define SBSW_PRGS_REQ_PROGRESS_REQ_MASK (0xFFFFU) 1154 #define SBSW_PRGS_REQ_PROGRESS_REQ_SHIFT (0U) 1155 #define SBSW_PRGS_REQ_PROGRESS_REQ_WIDTH (16U) 1156 #define SBSW_PRGS_REQ_PROGRESS_REQ(x) (((uint32_t)(((uint32_t)(x)) << SBSW_PRGS_REQ_PROGRESS_REQ_SHIFT)) & SBSW_PRGS_REQ_PROGRESS_REQ_MASK) 1157 1158 #define SBSW_PRGS_REQ_WRITTEN_MASK (0x10000U) 1159 #define SBSW_PRGS_REQ_WRITTEN_SHIFT (16U) 1160 #define SBSW_PRGS_REQ_WRITTEN_WIDTH (1U) 1161 #define SBSW_PRGS_REQ_WRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_PRGS_REQ_WRITTEN_SHIFT)) & SBSW_PRGS_REQ_WRITTEN_MASK) 1162 1163 #define SBSW_PRGS_REQ_OVERWRITTEN_MASK (0x20000U) 1164 #define SBSW_PRGS_REQ_OVERWRITTEN_SHIFT (17U) 1165 #define SBSW_PRGS_REQ_OVERWRITTEN_WIDTH (1U) 1166 #define SBSW_PRGS_REQ_OVERWRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_PRGS_REQ_OVERWRITTEN_SHIFT)) & SBSW_PRGS_REQ_OVERWRITTEN_MASK) 1167 /*! @} */ 1168 1169 /*! @name TC_ID - TMWDP Core Domain ID */ 1170 /*! @{ */ 1171 1172 #define SBSW_TC_ID_ID_MASK (0xFU) 1173 #define SBSW_TC_ID_ID_SHIFT (0U) 1174 #define SBSW_TC_ID_ID_WIDTH (4U) 1175 #define SBSW_TC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TC_ID_ID_SHIFT)) & SBSW_TC_ID_ID_MASK) 1176 1177 #define SBSW_TC_ID_WRITTEN_MASK (0x100U) 1178 #define SBSW_TC_ID_WRITTEN_SHIFT (8U) 1179 #define SBSW_TC_ID_WRITTEN_WIDTH (1U) 1180 #define SBSW_TC_ID_WRITTEN(x) (((uint32_t)(((uint32_t)(x)) << SBSW_TC_ID_WRITTEN_SHIFT)) & SBSW_TC_ID_WRITTEN_MASK) 1181 /*! @} */ 1182 1183 /*! 1184 * @} 1185 */ /* end of group SBSW_Register_Masks */ 1186 1187 /*! 1188 * @} 1189 */ /* end of group SBSW_Peripheral_Access_Layer */ 1190 1191 #endif /* #if !defined(S32Z2_SBSW_H_) */ 1192
