1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RTU_XRDC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_RTU_XRDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RTU_XRDC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RTU_XRDC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTU_XRDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTU_XRDC_Peripheral_Access_Layer RTU_XRDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTU_XRDC - Size of Registers Arrays */ 72 #define RTU_XRDC_MDAC_COUNT 13u 73 #define RTU_XRDC_MRC_COUNT 15u 74 #define RTU_XRDC_DERRLOC_COUNT 16u 75 #define RTU_XRDC_DERRW0_COUNT 19u 76 #define RTU_XRDC_PDAC_SLOT_PDACN_COUNT 43u 77 #define RTU_XRDC_PDAC_SLOT_COUNT 3u 78 #define RTU_XRDC_MRCN_COUNT 15u 79 #define RTU_XRDC_MRCN_MRGDN_COUNT 16u 80 81 /** RTU_XRDC - Register Layout Typedef */ 82 typedef struct { 83 __IO uint32_t CR; /**< Control, offset: 0x0 */ 84 uint8_t RESERVED_0[236]; 85 __I uint32_t HWCFG0; /**< Hardware Configuration 0, offset: 0xF0 */ 86 __I uint32_t HWCFG1; /**< Hardware Configuration 1, offset: 0xF4 */ 87 uint8_t RESERVED_1[8]; 88 __I uint8_t MDACFG[RTU_XRDC_MDAC_COUNT]; /**< Master Domain Assignment Configuration, array offset: 0x100, array step: 0x1 */ 89 uint8_t RESERVED_2[51]; 90 __I uint8_t MRCFG[RTU_XRDC_MRC_COUNT]; /**< Memory Region Configuration, array offset: 0x140, array step: 0x1 */ 91 uint8_t RESERVED_3[177]; 92 __I uint32_t DERRLOC[RTU_XRDC_DERRLOC_COUNT]; /**< Domain Error Location, array offset: 0x200, array step: 0x4 */ 93 uint8_t RESERVED_4[448]; 94 struct RTU_XRDC_DERRW0 { /* offset: 0x400, array step: 0x10 */ 95 __I uint32_t DERR_W0; /**< Domain Error Word 0, array offset: 0x400, array step: 0x10, valid indices: [0-14, 16-18] */ 96 __I uint32_t DERR_W1; /**< Domain Error Word 1, array offset: 0x404, array step: 0x10, valid indices: [0-14, 16-18] */ 97 uint8_t RESERVED_0[4]; 98 __O uint32_t DERR_W3; /**< Domain Error Word 3, array offset: 0x40C, array step: 0x10, valid indices: [0-14, 16-18] */ 99 } DERRW0[RTU_XRDC_DERRW0_COUNT]; 100 uint8_t RESERVED_5[720]; 101 __IO uint32_t MDA_W0_0_DFMT1; /**< Master Domain Assignment, offset: 0x800 */ 102 uint8_t RESERVED_6[28]; 103 __IO uint32_t MDA_W0_1_DFMT1; /**< Master Domain Assignment, offset: 0x820 */ 104 uint8_t RESERVED_7[28]; 105 __IO uint32_t MDA_W0_2_DFMT1; /**< Master Domain Assignment, offset: 0x840 */ 106 uint8_t RESERVED_8[28]; 107 __IO uint32_t MDA_W0_3_DFMT1; /**< Master Domain Assignment, offset: 0x860 */ 108 uint8_t RESERVED_9[28]; 109 __IO uint32_t MDA_W0_4_DFMT1; /**< Master Domain Assignment, offset: 0x880 */ 110 __IO uint32_t MDA_W1_4_DFMT1; /**< Master Domain Assignment, offset: 0x884 */ 111 __IO uint32_t MDA_W2_4_DFMT1; /**< Master Domain Assignment, offset: 0x888 */ 112 __IO uint32_t MDA_W3_4_DFMT1; /**< Master Domain Assignment, offset: 0x88C */ 113 __IO uint32_t MDA_W4_4_DFMT1; /**< Master Domain Assignment, offset: 0x890 */ 114 __IO uint32_t MDA_W5_4_DFMT1; /**< Master Domain Assignment, offset: 0x894 */ 115 __IO uint32_t MDA_W6_4_DFMT1; /**< Master Domain Assignment, offset: 0x898 */ 116 __IO uint32_t MDA_W7_4_DFMT1; /**< Master Domain Assignment, offset: 0x89C */ 117 __IO uint32_t MDA_W0_5_DFMT1; /**< Master Domain Assignment, offset: 0x8A0 */ 118 __IO uint32_t MDA_W1_5_DFMT1; /**< Master Domain Assignment, offset: 0x8A4 */ 119 __IO uint32_t MDA_W2_5_DFMT1; /**< Master Domain Assignment, offset: 0x8A8 */ 120 __IO uint32_t MDA_W3_5_DFMT1; /**< Master Domain Assignment, offset: 0x8AC */ 121 __IO uint32_t MDA_W4_5_DFMT1; /**< Master Domain Assignment, offset: 0x8B0 */ 122 __IO uint32_t MDA_W5_5_DFMT1; /**< Master Domain Assignment, offset: 0x8B4 */ 123 __IO uint32_t MDA_W6_5_DFMT1; /**< Master Domain Assignment, offset: 0x8B8 */ 124 __IO uint32_t MDA_W7_5_DFMT1; /**< Master Domain Assignment, offset: 0x8BC */ 125 __IO uint32_t MDA_W0_6_DFMT1; /**< Master Domain Assignment, offset: 0x8C0 */ 126 __IO uint32_t MDA_W1_6_DFMT1; /**< Master Domain Assignment, offset: 0x8C4 */ 127 __IO uint32_t MDA_W2_6_DFMT1; /**< Master Domain Assignment, offset: 0x8C8 */ 128 __IO uint32_t MDA_W3_6_DFMT1; /**< Master Domain Assignment, offset: 0x8CC */ 129 __IO uint32_t MDA_W4_6_DFMT1; /**< Master Domain Assignment, offset: 0x8D0 */ 130 __IO uint32_t MDA_W5_6_DFMT1; /**< Master Domain Assignment, offset: 0x8D4 */ 131 __IO uint32_t MDA_W6_6_DFMT1; /**< Master Domain Assignment, offset: 0x8D8 */ 132 __IO uint32_t MDA_W7_6_DFMT1; /**< Master Domain Assignment, offset: 0x8DC */ 133 __IO uint32_t MDA_W0_7_DFMT1; /**< Master Domain Assignment, offset: 0x8E0 */ 134 __IO uint32_t MDA_W1_7_DFMT1; /**< Master Domain Assignment, offset: 0x8E4 */ 135 __IO uint32_t MDA_W2_7_DFMT1; /**< Master Domain Assignment, offset: 0x8E8 */ 136 __IO uint32_t MDA_W3_7_DFMT1; /**< Master Domain Assignment, offset: 0x8EC */ 137 __IO uint32_t MDA_W4_7_DFMT1; /**< Master Domain Assignment, offset: 0x8F0 */ 138 __IO uint32_t MDA_W5_7_DFMT1; /**< Master Domain Assignment, offset: 0x8F4 */ 139 __IO uint32_t MDA_W6_7_DFMT1; /**< Master Domain Assignment, offset: 0x8F8 */ 140 __IO uint32_t MDA_W7_7_DFMT1; /**< Master Domain Assignment, offset: 0x8FC */ 141 __IO uint32_t MDA_W0_8_DFMT1; /**< Master Domain Assignment, offset: 0x900 */ 142 __IO uint32_t MDA_W1_8_DFMT1; /**< Master Domain Assignment, offset: 0x904 */ 143 __IO uint32_t MDA_W2_8_DFMT1; /**< Master Domain Assignment, offset: 0x908 */ 144 __IO uint32_t MDA_W3_8_DFMT1; /**< Master Domain Assignment, offset: 0x90C */ 145 __IO uint32_t MDA_W4_8_DFMT1; /**< Master Domain Assignment, offset: 0x910 */ 146 __IO uint32_t MDA_W5_8_DFMT1; /**< Master Domain Assignment, offset: 0x914 */ 147 __IO uint32_t MDA_W6_8_DFMT1; /**< Master Domain Assignment, offset: 0x918 */ 148 __IO uint32_t MDA_W7_8_DFMT1; /**< Master Domain Assignment, offset: 0x91C */ 149 __IO uint32_t MDA_W0_9_DFMT1; /**< Master Domain Assignment, offset: 0x920 */ 150 __IO uint32_t MDA_W1_9_DFMT1; /**< Master Domain Assignment, offset: 0x924 */ 151 __IO uint32_t MDA_W2_9_DFMT1; /**< Master Domain Assignment, offset: 0x928 */ 152 __IO uint32_t MDA_W3_9_DFMT1; /**< Master Domain Assignment, offset: 0x92C */ 153 __IO uint32_t MDA_W4_9_DFMT1; /**< Master Domain Assignment, offset: 0x930 */ 154 __IO uint32_t MDA_W5_9_DFMT1; /**< Master Domain Assignment, offset: 0x934 */ 155 __IO uint32_t MDA_W6_9_DFMT1; /**< Master Domain Assignment, offset: 0x938 */ 156 __IO uint32_t MDA_W7_9_DFMT1; /**< Master Domain Assignment, offset: 0x93C */ 157 __IO uint32_t MDA_W0_10_DFMT1; /**< Master Domain Assignment, offset: 0x940 */ 158 __IO uint32_t MDA_W1_10_DFMT1; /**< Master Domain Assignment, offset: 0x944 */ 159 __IO uint32_t MDA_W2_10_DFMT1; /**< Master Domain Assignment, offset: 0x948 */ 160 __IO uint32_t MDA_W3_10_DFMT1; /**< Master Domain Assignment, offset: 0x94C */ 161 __IO uint32_t MDA_W4_10_DFMT1; /**< Master Domain Assignment, offset: 0x950 */ 162 __IO uint32_t MDA_W5_10_DFMT1; /**< Master Domain Assignment, offset: 0x954 */ 163 __IO uint32_t MDA_W6_10_DFMT1; /**< Master Domain Assignment, offset: 0x958 */ 164 __IO uint32_t MDA_W7_10_DFMT1; /**< Master Domain Assignment, offset: 0x95C */ 165 __IO uint32_t MDA_W0_11_DFMT1; /**< Master Domain Assignment, offset: 0x960 */ 166 __IO uint32_t MDA_W1_11_DFMT1; /**< Master Domain Assignment, offset: 0x964 */ 167 __IO uint32_t MDA_W2_11_DFMT1; /**< Master Domain Assignment, offset: 0x968 */ 168 __IO uint32_t MDA_W3_11_DFMT1; /**< Master Domain Assignment, offset: 0x96C */ 169 __IO uint32_t MDA_W4_11_DFMT1; /**< Master Domain Assignment, offset: 0x970 */ 170 __IO uint32_t MDA_W5_11_DFMT1; /**< Master Domain Assignment, offset: 0x974 */ 171 __IO uint32_t MDA_W6_11_DFMT1; /**< Master Domain Assignment, offset: 0x978 */ 172 __IO uint32_t MDA_W7_11_DFMT1; /**< Master Domain Assignment, offset: 0x97C */ 173 __IO uint32_t MDA_W0_12_DFMT1; /**< Master Domain Assignment, offset: 0x980 */ 174 uint8_t RESERVED_10[1660]; 175 struct RTU_XRDC_PDAC_SLOT { /* offset: 0x1000, array step: 0x400 */ 176 struct RTU_XRDC_PDAC_SLOT_PDACN { /* offset: 0x1000, array step: index*0x400, index2*0x8 */ 177 __IO uint32_t PDAC_W0; /**< Peripheral Domain Access Control Word 0, array offset: 0x1000, array step: index*0x400, index2*0x8, valid indices: [0][0-15, 18-29, 31-42], [1][0-8, 10-17, 21-24], [2][0-7, 9, 12-15, 18-29, 31-42] */ 178 __IO uint32_t PDAC_W1; /**< Peripheral Domain Access Control Word 1, array offset: 0x1004, array step: index*0x400, index2*0x8, valid indices: [0][0-15, 18-29, 31-42], [1][0-8, 10-17, 21-24], [2][0-7, 9, 12-15, 18-29, 31-42] */ 179 } PDACN[RTU_XRDC_PDAC_SLOT_PDACN_COUNT]; 180 uint8_t RESERVED_0[680]; 181 } PDAC_SLOT[RTU_XRDC_PDAC_SLOT_COUNT]; 182 uint8_t RESERVED_11[1024]; 183 struct RTU_XRDC_MRGDN { /* offset: 0x2000, array step: index*0x200, index2*0x20 */ 184 __IO uint32_t XRDC_MRGD_W0; /**< Memory Region Descriptor Word 0, array offset: 0x2000, array step: index*0x200, index2*0x20 */ 185 __IO uint32_t XRDC_MRGD_W1; /**< Memory Region Descriptor Word 1, array offset: 0x2004, array step: index*0x200, index2*0x20 */ 186 __IO uint32_t XRDC_MRGD_W2; /**< Memory Region Descriptor Word 2, array offset: 0x2008, array step: index*0x200, index2*0x20 */ 187 __IO uint32_t XRDC_MRGD_W3; /**< Memory Region Descriptor Word 3, array offset: 0x200C, array step: index*0x200, index2*0x20 */ 188 uint8_t RESERVED_0[16]; 189 } MRGDN[RTU_XRDC_MRCN_COUNT][RTU_XRDC_MRCN_MRGDN_COUNT]; 190 } RTU_XRDC_Type, *RTU_XRDC_MemMapPtr; 191 192 /** Number of instances of the RTU_XRDC module. */ 193 #define RTU_XRDC_INSTANCE_COUNT (2u) 194 195 /* RTU_XRDC - Peripheral instance base addresses */ 196 /** Peripheral RTU0__XRDC base address */ 197 #define IP_RTU0__XRDC_BASE (0x76100000u) 198 /** Peripheral RTU0__XRDC base pointer */ 199 #define IP_RTU0__XRDC ((RTU_XRDC_Type *)IP_RTU0__XRDC_BASE) 200 /** Peripheral RTU1__XRDC base address */ 201 #define IP_RTU1__XRDC_BASE (0x76900000u) 202 /** Peripheral RTU1__XRDC base pointer */ 203 #define IP_RTU1__XRDC ((RTU_XRDC_Type *)IP_RTU1__XRDC_BASE) 204 /** Array initializer of RTU_XRDC peripheral base addresses */ 205 #define IP_RTU_XRDC_BASE_ADDRS { IP_RTU0__XRDC_BASE, IP_RTU1__XRDC_BASE } 206 /** Array initializer of RTU_XRDC peripheral base pointers */ 207 #define IP_RTU_XRDC_BASE_PTRS { IP_RTU0__XRDC, IP_RTU1__XRDC } 208 209 /* ---------------------------------------------------------------------------- 210 -- RTU_XRDC Register Masks 211 ---------------------------------------------------------------------------- */ 212 213 /*! 214 * @addtogroup RTU_XRDC_Register_Masks RTU_XRDC Register Masks 215 * @{ 216 */ 217 218 /*! @name CR - Control */ 219 /*! @{ */ 220 221 #define RTU_XRDC_CR_GVLD_MASK (0x1U) 222 #define RTU_XRDC_CR_GVLD_SHIFT (0U) 223 #define RTU_XRDC_CR_GVLD_WIDTH (1U) 224 #define RTU_XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_CR_GVLD_SHIFT)) & RTU_XRDC_CR_GVLD_MASK) 225 226 #define RTU_XRDC_CR_HRL_MASK (0x1EU) 227 #define RTU_XRDC_CR_HRL_SHIFT (1U) 228 #define RTU_XRDC_CR_HRL_WIDTH (4U) 229 #define RTU_XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_CR_HRL_SHIFT)) & RTU_XRDC_CR_HRL_MASK) 230 231 #define RTU_XRDC_CR_MRF_MASK (0x80U) 232 #define RTU_XRDC_CR_MRF_SHIFT (7U) 233 #define RTU_XRDC_CR_MRF_WIDTH (1U) 234 #define RTU_XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_CR_MRF_SHIFT)) & RTU_XRDC_CR_MRF_MASK) 235 236 #define RTU_XRDC_CR_VAW_MASK (0x100U) 237 #define RTU_XRDC_CR_VAW_SHIFT (8U) 238 #define RTU_XRDC_CR_VAW_WIDTH (1U) 239 #define RTU_XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_CR_VAW_SHIFT)) & RTU_XRDC_CR_VAW_MASK) 240 241 #define RTU_XRDC_CR_LK1_MASK (0x40000000U) 242 #define RTU_XRDC_CR_LK1_SHIFT (30U) 243 #define RTU_XRDC_CR_LK1_WIDTH (1U) 244 #define RTU_XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_CR_LK1_SHIFT)) & RTU_XRDC_CR_LK1_MASK) 245 /*! @} */ 246 247 /*! @name HWCFG0 - Hardware Configuration 0 */ 248 /*! @{ */ 249 250 #define RTU_XRDC_HWCFG0_NDID_MASK (0xFFU) 251 #define RTU_XRDC_HWCFG0_NDID_SHIFT (0U) 252 #define RTU_XRDC_HWCFG0_NDID_WIDTH (8U) 253 #define RTU_XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG0_NDID_SHIFT)) & RTU_XRDC_HWCFG0_NDID_MASK) 254 255 #define RTU_XRDC_HWCFG0_NMSTR_MASK (0xFF00U) 256 #define RTU_XRDC_HWCFG0_NMSTR_SHIFT (8U) 257 #define RTU_XRDC_HWCFG0_NMSTR_WIDTH (8U) 258 #define RTU_XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG0_NMSTR_SHIFT)) & RTU_XRDC_HWCFG0_NMSTR_MASK) 259 260 #define RTU_XRDC_HWCFG0_NMRC_MASK (0xFF0000U) 261 #define RTU_XRDC_HWCFG0_NMRC_SHIFT (16U) 262 #define RTU_XRDC_HWCFG0_NMRC_WIDTH (8U) 263 #define RTU_XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG0_NMRC_SHIFT)) & RTU_XRDC_HWCFG0_NMRC_MASK) 264 265 #define RTU_XRDC_HWCFG0_NPAC_MASK (0xF000000U) 266 #define RTU_XRDC_HWCFG0_NPAC_SHIFT (24U) 267 #define RTU_XRDC_HWCFG0_NPAC_WIDTH (4U) 268 #define RTU_XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG0_NPAC_SHIFT)) & RTU_XRDC_HWCFG0_NPAC_MASK) 269 270 #define RTU_XRDC_HWCFG0_MID_MASK (0xF0000000U) 271 #define RTU_XRDC_HWCFG0_MID_SHIFT (28U) 272 #define RTU_XRDC_HWCFG0_MID_WIDTH (4U) 273 #define RTU_XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG0_MID_SHIFT)) & RTU_XRDC_HWCFG0_MID_MASK) 274 /*! @} */ 275 276 /*! @name HWCFG1 - Hardware Configuration 1 */ 277 /*! @{ */ 278 279 #define RTU_XRDC_HWCFG1_DID_MASK (0xFU) 280 #define RTU_XRDC_HWCFG1_DID_SHIFT (0U) 281 #define RTU_XRDC_HWCFG1_DID_WIDTH (4U) 282 #define RTU_XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_HWCFG1_DID_SHIFT)) & RTU_XRDC_HWCFG1_DID_MASK) 283 /*! @} */ 284 285 /*! @name MDACFG - Master Domain Assignment Configuration */ 286 /*! @{ */ 287 288 #define RTU_XRDC_MDACFG_NMDAR_MASK (0xFU) 289 #define RTU_XRDC_MDACFG_NMDAR_SHIFT (0U) 290 #define RTU_XRDC_MDACFG_NMDAR_WIDTH (4U) 291 #define RTU_XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << RTU_XRDC_MDACFG_NMDAR_SHIFT)) & RTU_XRDC_MDACFG_NMDAR_MASK) 292 293 #define RTU_XRDC_MDACFG_NCM_MASK (0x80U) 294 #define RTU_XRDC_MDACFG_NCM_SHIFT (7U) 295 #define RTU_XRDC_MDACFG_NCM_WIDTH (1U) 296 #define RTU_XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << RTU_XRDC_MDACFG_NCM_SHIFT)) & RTU_XRDC_MDACFG_NCM_MASK) 297 /*! @} */ 298 299 /*! @name MRCFG - Memory Region Configuration */ 300 /*! @{ */ 301 302 #define RTU_XRDC_MRCFG_NMRGD_MASK (0x1FU) 303 #define RTU_XRDC_MRCFG_NMRGD_SHIFT (0U) 304 #define RTU_XRDC_MRCFG_NMRGD_WIDTH (5U) 305 #define RTU_XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << RTU_XRDC_MRCFG_NMRGD_SHIFT)) & RTU_XRDC_MRCFG_NMRGD_MASK) 306 /*! @} */ 307 308 /*! @name DERRLOC - Domain Error Location */ 309 /*! @{ */ 310 311 #define RTU_XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) 312 #define RTU_XRDC_DERRLOC_MRCINST_SHIFT (0U) 313 #define RTU_XRDC_DERRLOC_MRCINST_WIDTH (16U) 314 #define RTU_XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERRLOC_MRCINST_SHIFT)) & RTU_XRDC_DERRLOC_MRCINST_MASK) 315 316 #define RTU_XRDC_DERRLOC_PACINST_MASK (0xF0000U) 317 #define RTU_XRDC_DERRLOC_PACINST_SHIFT (16U) 318 #define RTU_XRDC_DERRLOC_PACINST_WIDTH (4U) 319 #define RTU_XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERRLOC_PACINST_SHIFT)) & RTU_XRDC_DERRLOC_PACINST_MASK) 320 /*! @} */ 321 322 /*! @name DERR_W0 - Domain Error Word 0 */ 323 /*! @{ */ 324 325 #define RTU_XRDC_DERR_W0_EADDR_MASK (0xFFFFFFFFU) 326 #define RTU_XRDC_DERR_W0_EADDR_SHIFT (0U) 327 #define RTU_XRDC_DERR_W0_EADDR_WIDTH (32U) 328 #define RTU_XRDC_DERR_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W0_EADDR_SHIFT)) & RTU_XRDC_DERR_W0_EADDR_MASK) 329 /*! @} */ 330 331 /*! @name DERR_W1 - Domain Error Word 1 */ 332 /*! @{ */ 333 334 #define RTU_XRDC_DERR_W1_EDID_MASK (0xFU) 335 #define RTU_XRDC_DERR_W1_EDID_SHIFT (0U) 336 #define RTU_XRDC_DERR_W1_EDID_WIDTH (4U) 337 #define RTU_XRDC_DERR_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W1_EDID_SHIFT)) & RTU_XRDC_DERR_W1_EDID_MASK) 338 339 #define RTU_XRDC_DERR_W1_EATR_MASK (0x700U) 340 #define RTU_XRDC_DERR_W1_EATR_SHIFT (8U) 341 #define RTU_XRDC_DERR_W1_EATR_WIDTH (3U) 342 #define RTU_XRDC_DERR_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W1_EATR_SHIFT)) & RTU_XRDC_DERR_W1_EATR_MASK) 343 344 #define RTU_XRDC_DERR_W1_ERW_MASK (0x800U) 345 #define RTU_XRDC_DERR_W1_ERW_SHIFT (11U) 346 #define RTU_XRDC_DERR_W1_ERW_WIDTH (1U) 347 #define RTU_XRDC_DERR_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W1_ERW_SHIFT)) & RTU_XRDC_DERR_W1_ERW_MASK) 348 349 #define RTU_XRDC_DERR_W1_EPORT_MASK (0x7000000U) 350 #define RTU_XRDC_DERR_W1_EPORT_SHIFT (24U) 351 #define RTU_XRDC_DERR_W1_EPORT_WIDTH (3U) 352 #define RTU_XRDC_DERR_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W1_EPORT_SHIFT)) & RTU_XRDC_DERR_W1_EPORT_MASK) 353 354 #define RTU_XRDC_DERR_W1_EST_MASK (0xC0000000U) 355 #define RTU_XRDC_DERR_W1_EST_SHIFT (30U) 356 #define RTU_XRDC_DERR_W1_EST_WIDTH (2U) 357 #define RTU_XRDC_DERR_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W1_EST_SHIFT)) & RTU_XRDC_DERR_W1_EST_MASK) 358 /*! @} */ 359 360 /*! @name DERR_W3 - Domain Error Word 3 */ 361 /*! @{ */ 362 363 #define RTU_XRDC_DERR_W3_RECR_MASK (0xC0000000U) 364 #define RTU_XRDC_DERR_W3_RECR_SHIFT (30U) 365 #define RTU_XRDC_DERR_W3_RECR_WIDTH (2U) 366 #define RTU_XRDC_DERR_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_DERR_W3_RECR_SHIFT)) & RTU_XRDC_DERR_W3_RECR_MASK) 367 /*! @} */ 368 369 /*! @name MDA_W0_0_DFMT1 - Master Domain Assignment */ 370 /*! @{ */ 371 372 #define RTU_XRDC_MDA_W0_0_DFMT1_DID_MASK (0xFU) 373 #define RTU_XRDC_MDA_W0_0_DFMT1_DID_SHIFT (0U) 374 #define RTU_XRDC_MDA_W0_0_DFMT1_DID_WIDTH (4U) 375 #define RTU_XRDC_MDA_W0_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_DID_MASK) 376 377 #define RTU_XRDC_MDA_W0_0_DFMT1_PA_MASK (0x30U) 378 #define RTU_XRDC_MDA_W0_0_DFMT1_PA_SHIFT (4U) 379 #define RTU_XRDC_MDA_W0_0_DFMT1_PA_WIDTH (2U) 380 #define RTU_XRDC_MDA_W0_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_PA_MASK) 381 382 #define RTU_XRDC_MDA_W0_0_DFMT1_SA_MASK (0xC0U) 383 #define RTU_XRDC_MDA_W0_0_DFMT1_SA_SHIFT (6U) 384 #define RTU_XRDC_MDA_W0_0_DFMT1_SA_WIDTH (2U) 385 #define RTU_XRDC_MDA_W0_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_SA_MASK) 386 387 #define RTU_XRDC_MDA_W0_0_DFMT1_DIDB_MASK (0x100U) 388 #define RTU_XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT (8U) 389 #define RTU_XRDC_MDA_W0_0_DFMT1_DIDB_WIDTH (1U) 390 #define RTU_XRDC_MDA_W0_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_DIDB_MASK) 391 392 #define RTU_XRDC_MDA_W0_0_DFMT1_DFMT_MASK (0x20000000U) 393 #define RTU_XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT (29U) 394 #define RTU_XRDC_MDA_W0_0_DFMT1_DFMT_WIDTH (1U) 395 #define RTU_XRDC_MDA_W0_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_DFMT_MASK) 396 397 #define RTU_XRDC_MDA_W0_0_DFMT1_LK1_MASK (0x40000000U) 398 #define RTU_XRDC_MDA_W0_0_DFMT1_LK1_SHIFT (30U) 399 #define RTU_XRDC_MDA_W0_0_DFMT1_LK1_WIDTH (1U) 400 #define RTU_XRDC_MDA_W0_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_LK1_MASK) 401 402 #define RTU_XRDC_MDA_W0_0_DFMT1_VLD_MASK (0x80000000U) 403 #define RTU_XRDC_MDA_W0_0_DFMT1_VLD_SHIFT (31U) 404 #define RTU_XRDC_MDA_W0_0_DFMT1_VLD_WIDTH (1U) 405 #define RTU_XRDC_MDA_W0_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_0_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_0_DFMT1_VLD_MASK) 406 /*! @} */ 407 408 /*! @name MDA_W0_1_DFMT1 - Master Domain Assignment */ 409 /*! @{ */ 410 411 #define RTU_XRDC_MDA_W0_1_DFMT1_DID_MASK (0xFU) 412 #define RTU_XRDC_MDA_W0_1_DFMT1_DID_SHIFT (0U) 413 #define RTU_XRDC_MDA_W0_1_DFMT1_DID_WIDTH (4U) 414 #define RTU_XRDC_MDA_W0_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_DID_MASK) 415 416 #define RTU_XRDC_MDA_W0_1_DFMT1_PA_MASK (0x30U) 417 #define RTU_XRDC_MDA_W0_1_DFMT1_PA_SHIFT (4U) 418 #define RTU_XRDC_MDA_W0_1_DFMT1_PA_WIDTH (2U) 419 #define RTU_XRDC_MDA_W0_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_PA_MASK) 420 421 #define RTU_XRDC_MDA_W0_1_DFMT1_SA_MASK (0xC0U) 422 #define RTU_XRDC_MDA_W0_1_DFMT1_SA_SHIFT (6U) 423 #define RTU_XRDC_MDA_W0_1_DFMT1_SA_WIDTH (2U) 424 #define RTU_XRDC_MDA_W0_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_SA_MASK) 425 426 #define RTU_XRDC_MDA_W0_1_DFMT1_DIDB_MASK (0x100U) 427 #define RTU_XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT (8U) 428 #define RTU_XRDC_MDA_W0_1_DFMT1_DIDB_WIDTH (1U) 429 #define RTU_XRDC_MDA_W0_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_DIDB_MASK) 430 431 #define RTU_XRDC_MDA_W0_1_DFMT1_DFMT_MASK (0x20000000U) 432 #define RTU_XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT (29U) 433 #define RTU_XRDC_MDA_W0_1_DFMT1_DFMT_WIDTH (1U) 434 #define RTU_XRDC_MDA_W0_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_DFMT_MASK) 435 436 #define RTU_XRDC_MDA_W0_1_DFMT1_LK1_MASK (0x40000000U) 437 #define RTU_XRDC_MDA_W0_1_DFMT1_LK1_SHIFT (30U) 438 #define RTU_XRDC_MDA_W0_1_DFMT1_LK1_WIDTH (1U) 439 #define RTU_XRDC_MDA_W0_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_LK1_MASK) 440 441 #define RTU_XRDC_MDA_W0_1_DFMT1_VLD_MASK (0x80000000U) 442 #define RTU_XRDC_MDA_W0_1_DFMT1_VLD_SHIFT (31U) 443 #define RTU_XRDC_MDA_W0_1_DFMT1_VLD_WIDTH (1U) 444 #define RTU_XRDC_MDA_W0_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_1_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_1_DFMT1_VLD_MASK) 445 /*! @} */ 446 447 /*! @name MDA_W0_2_DFMT1 - Master Domain Assignment */ 448 /*! @{ */ 449 450 #define RTU_XRDC_MDA_W0_2_DFMT1_DID_MASK (0xFU) 451 #define RTU_XRDC_MDA_W0_2_DFMT1_DID_SHIFT (0U) 452 #define RTU_XRDC_MDA_W0_2_DFMT1_DID_WIDTH (4U) 453 #define RTU_XRDC_MDA_W0_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_DID_MASK) 454 455 #define RTU_XRDC_MDA_W0_2_DFMT1_PA_MASK (0x30U) 456 #define RTU_XRDC_MDA_W0_2_DFMT1_PA_SHIFT (4U) 457 #define RTU_XRDC_MDA_W0_2_DFMT1_PA_WIDTH (2U) 458 #define RTU_XRDC_MDA_W0_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_PA_MASK) 459 460 #define RTU_XRDC_MDA_W0_2_DFMT1_SA_MASK (0xC0U) 461 #define RTU_XRDC_MDA_W0_2_DFMT1_SA_SHIFT (6U) 462 #define RTU_XRDC_MDA_W0_2_DFMT1_SA_WIDTH (2U) 463 #define RTU_XRDC_MDA_W0_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_SA_MASK) 464 465 #define RTU_XRDC_MDA_W0_2_DFMT1_DIDB_MASK (0x100U) 466 #define RTU_XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT (8U) 467 #define RTU_XRDC_MDA_W0_2_DFMT1_DIDB_WIDTH (1U) 468 #define RTU_XRDC_MDA_W0_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_DIDB_MASK) 469 470 #define RTU_XRDC_MDA_W0_2_DFMT1_DFMT_MASK (0x20000000U) 471 #define RTU_XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT (29U) 472 #define RTU_XRDC_MDA_W0_2_DFMT1_DFMT_WIDTH (1U) 473 #define RTU_XRDC_MDA_W0_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_DFMT_MASK) 474 475 #define RTU_XRDC_MDA_W0_2_DFMT1_LK1_MASK (0x40000000U) 476 #define RTU_XRDC_MDA_W0_2_DFMT1_LK1_SHIFT (30U) 477 #define RTU_XRDC_MDA_W0_2_DFMT1_LK1_WIDTH (1U) 478 #define RTU_XRDC_MDA_W0_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_LK1_MASK) 479 480 #define RTU_XRDC_MDA_W0_2_DFMT1_VLD_MASK (0x80000000U) 481 #define RTU_XRDC_MDA_W0_2_DFMT1_VLD_SHIFT (31U) 482 #define RTU_XRDC_MDA_W0_2_DFMT1_VLD_WIDTH (1U) 483 #define RTU_XRDC_MDA_W0_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_2_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_2_DFMT1_VLD_MASK) 484 /*! @} */ 485 486 /*! @name MDA_W0_3_DFMT1 - Master Domain Assignment */ 487 /*! @{ */ 488 489 #define RTU_XRDC_MDA_W0_3_DFMT1_DID_MASK (0xFU) 490 #define RTU_XRDC_MDA_W0_3_DFMT1_DID_SHIFT (0U) 491 #define RTU_XRDC_MDA_W0_3_DFMT1_DID_WIDTH (4U) 492 #define RTU_XRDC_MDA_W0_3_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_DID_MASK) 493 494 #define RTU_XRDC_MDA_W0_3_DFMT1_PA_MASK (0x30U) 495 #define RTU_XRDC_MDA_W0_3_DFMT1_PA_SHIFT (4U) 496 #define RTU_XRDC_MDA_W0_3_DFMT1_PA_WIDTH (2U) 497 #define RTU_XRDC_MDA_W0_3_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_PA_MASK) 498 499 #define RTU_XRDC_MDA_W0_3_DFMT1_SA_MASK (0xC0U) 500 #define RTU_XRDC_MDA_W0_3_DFMT1_SA_SHIFT (6U) 501 #define RTU_XRDC_MDA_W0_3_DFMT1_SA_WIDTH (2U) 502 #define RTU_XRDC_MDA_W0_3_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_SA_MASK) 503 504 #define RTU_XRDC_MDA_W0_3_DFMT1_DIDB_MASK (0x100U) 505 #define RTU_XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT (8U) 506 #define RTU_XRDC_MDA_W0_3_DFMT1_DIDB_WIDTH (1U) 507 #define RTU_XRDC_MDA_W0_3_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_DIDB_MASK) 508 509 #define RTU_XRDC_MDA_W0_3_DFMT1_DFMT_MASK (0x20000000U) 510 #define RTU_XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT (29U) 511 #define RTU_XRDC_MDA_W0_3_DFMT1_DFMT_WIDTH (1U) 512 #define RTU_XRDC_MDA_W0_3_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_DFMT_MASK) 513 514 #define RTU_XRDC_MDA_W0_3_DFMT1_LK1_MASK (0x40000000U) 515 #define RTU_XRDC_MDA_W0_3_DFMT1_LK1_SHIFT (30U) 516 #define RTU_XRDC_MDA_W0_3_DFMT1_LK1_WIDTH (1U) 517 #define RTU_XRDC_MDA_W0_3_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_LK1_MASK) 518 519 #define RTU_XRDC_MDA_W0_3_DFMT1_VLD_MASK (0x80000000U) 520 #define RTU_XRDC_MDA_W0_3_DFMT1_VLD_SHIFT (31U) 521 #define RTU_XRDC_MDA_W0_3_DFMT1_VLD_WIDTH (1U) 522 #define RTU_XRDC_MDA_W0_3_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_3_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_3_DFMT1_VLD_MASK) 523 /*! @} */ 524 525 /*! @name MDA_W0_4_DFMT1 - Master Domain Assignment */ 526 /*! @{ */ 527 528 #define RTU_XRDC_MDA_W0_4_DFMT1_DID_MASK (0xFU) 529 #define RTU_XRDC_MDA_W0_4_DFMT1_DID_SHIFT (0U) 530 #define RTU_XRDC_MDA_W0_4_DFMT1_DID_WIDTH (4U) 531 #define RTU_XRDC_MDA_W0_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_DID_MASK) 532 533 #define RTU_XRDC_MDA_W0_4_DFMT1_PA_MASK (0x30U) 534 #define RTU_XRDC_MDA_W0_4_DFMT1_PA_SHIFT (4U) 535 #define RTU_XRDC_MDA_W0_4_DFMT1_PA_WIDTH (2U) 536 #define RTU_XRDC_MDA_W0_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_PA_MASK) 537 538 #define RTU_XRDC_MDA_W0_4_DFMT1_SA_MASK (0xC0U) 539 #define RTU_XRDC_MDA_W0_4_DFMT1_SA_SHIFT (6U) 540 #define RTU_XRDC_MDA_W0_4_DFMT1_SA_WIDTH (2U) 541 #define RTU_XRDC_MDA_W0_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_SA_MASK) 542 543 #define RTU_XRDC_MDA_W0_4_DFMT1_DIDB_MASK (0x100U) 544 #define RTU_XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT (8U) 545 #define RTU_XRDC_MDA_W0_4_DFMT1_DIDB_WIDTH (1U) 546 #define RTU_XRDC_MDA_W0_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_DIDB_MASK) 547 548 #define RTU_XRDC_MDA_W0_4_DFMT1_LPID_MASK (0xF000000U) 549 #define RTU_XRDC_MDA_W0_4_DFMT1_LPID_SHIFT (24U) 550 #define RTU_XRDC_MDA_W0_4_DFMT1_LPID_WIDTH (4U) 551 #define RTU_XRDC_MDA_W0_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_LPID_MASK) 552 553 #define RTU_XRDC_MDA_W0_4_DFMT1_LPE_MASK (0x10000000U) 554 #define RTU_XRDC_MDA_W0_4_DFMT1_LPE_SHIFT (28U) 555 #define RTU_XRDC_MDA_W0_4_DFMT1_LPE_WIDTH (1U) 556 #define RTU_XRDC_MDA_W0_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_LPE_MASK) 557 558 #define RTU_XRDC_MDA_W0_4_DFMT1_DFMT_MASK (0x20000000U) 559 #define RTU_XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT (29U) 560 #define RTU_XRDC_MDA_W0_4_DFMT1_DFMT_WIDTH (1U) 561 #define RTU_XRDC_MDA_W0_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_DFMT_MASK) 562 563 #define RTU_XRDC_MDA_W0_4_DFMT1_LK1_MASK (0x40000000U) 564 #define RTU_XRDC_MDA_W0_4_DFMT1_LK1_SHIFT (30U) 565 #define RTU_XRDC_MDA_W0_4_DFMT1_LK1_WIDTH (1U) 566 #define RTU_XRDC_MDA_W0_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_LK1_MASK) 567 568 #define RTU_XRDC_MDA_W0_4_DFMT1_VLD_MASK (0x80000000U) 569 #define RTU_XRDC_MDA_W0_4_DFMT1_VLD_SHIFT (31U) 570 #define RTU_XRDC_MDA_W0_4_DFMT1_VLD_WIDTH (1U) 571 #define RTU_XRDC_MDA_W0_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_4_DFMT1_VLD_MASK) 572 /*! @} */ 573 574 /*! @name MDA_W1_4_DFMT1 - Master Domain Assignment */ 575 /*! @{ */ 576 577 #define RTU_XRDC_MDA_W1_4_DFMT1_DID_MASK (0xFU) 578 #define RTU_XRDC_MDA_W1_4_DFMT1_DID_SHIFT (0U) 579 #define RTU_XRDC_MDA_W1_4_DFMT1_DID_WIDTH (4U) 580 #define RTU_XRDC_MDA_W1_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_DID_MASK) 581 582 #define RTU_XRDC_MDA_W1_4_DFMT1_PA_MASK (0x30U) 583 #define RTU_XRDC_MDA_W1_4_DFMT1_PA_SHIFT (4U) 584 #define RTU_XRDC_MDA_W1_4_DFMT1_PA_WIDTH (2U) 585 #define RTU_XRDC_MDA_W1_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_PA_MASK) 586 587 #define RTU_XRDC_MDA_W1_4_DFMT1_SA_MASK (0xC0U) 588 #define RTU_XRDC_MDA_W1_4_DFMT1_SA_SHIFT (6U) 589 #define RTU_XRDC_MDA_W1_4_DFMT1_SA_WIDTH (2U) 590 #define RTU_XRDC_MDA_W1_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_SA_MASK) 591 592 #define RTU_XRDC_MDA_W1_4_DFMT1_DIDB_MASK (0x100U) 593 #define RTU_XRDC_MDA_W1_4_DFMT1_DIDB_SHIFT (8U) 594 #define RTU_XRDC_MDA_W1_4_DFMT1_DIDB_WIDTH (1U) 595 #define RTU_XRDC_MDA_W1_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_DIDB_MASK) 596 597 #define RTU_XRDC_MDA_W1_4_DFMT1_LPID_MASK (0xF000000U) 598 #define RTU_XRDC_MDA_W1_4_DFMT1_LPID_SHIFT (24U) 599 #define RTU_XRDC_MDA_W1_4_DFMT1_LPID_WIDTH (4U) 600 #define RTU_XRDC_MDA_W1_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_LPID_MASK) 601 602 #define RTU_XRDC_MDA_W1_4_DFMT1_LPE_MASK (0x10000000U) 603 #define RTU_XRDC_MDA_W1_4_DFMT1_LPE_SHIFT (28U) 604 #define RTU_XRDC_MDA_W1_4_DFMT1_LPE_WIDTH (1U) 605 #define RTU_XRDC_MDA_W1_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_LPE_MASK) 606 607 #define RTU_XRDC_MDA_W1_4_DFMT1_DFMT_MASK (0x20000000U) 608 #define RTU_XRDC_MDA_W1_4_DFMT1_DFMT_SHIFT (29U) 609 #define RTU_XRDC_MDA_W1_4_DFMT1_DFMT_WIDTH (1U) 610 #define RTU_XRDC_MDA_W1_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_DFMT_MASK) 611 612 #define RTU_XRDC_MDA_W1_4_DFMT1_LK1_MASK (0x40000000U) 613 #define RTU_XRDC_MDA_W1_4_DFMT1_LK1_SHIFT (30U) 614 #define RTU_XRDC_MDA_W1_4_DFMT1_LK1_WIDTH (1U) 615 #define RTU_XRDC_MDA_W1_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_LK1_MASK) 616 617 #define RTU_XRDC_MDA_W1_4_DFMT1_VLD_MASK (0x80000000U) 618 #define RTU_XRDC_MDA_W1_4_DFMT1_VLD_SHIFT (31U) 619 #define RTU_XRDC_MDA_W1_4_DFMT1_VLD_WIDTH (1U) 620 #define RTU_XRDC_MDA_W1_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_4_DFMT1_VLD_MASK) 621 /*! @} */ 622 623 /*! @name MDA_W2_4_DFMT1 - Master Domain Assignment */ 624 /*! @{ */ 625 626 #define RTU_XRDC_MDA_W2_4_DFMT1_DID_MASK (0xFU) 627 #define RTU_XRDC_MDA_W2_4_DFMT1_DID_SHIFT (0U) 628 #define RTU_XRDC_MDA_W2_4_DFMT1_DID_WIDTH (4U) 629 #define RTU_XRDC_MDA_W2_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_DID_MASK) 630 631 #define RTU_XRDC_MDA_W2_4_DFMT1_PA_MASK (0x30U) 632 #define RTU_XRDC_MDA_W2_4_DFMT1_PA_SHIFT (4U) 633 #define RTU_XRDC_MDA_W2_4_DFMT1_PA_WIDTH (2U) 634 #define RTU_XRDC_MDA_W2_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_PA_MASK) 635 636 #define RTU_XRDC_MDA_W2_4_DFMT1_SA_MASK (0xC0U) 637 #define RTU_XRDC_MDA_W2_4_DFMT1_SA_SHIFT (6U) 638 #define RTU_XRDC_MDA_W2_4_DFMT1_SA_WIDTH (2U) 639 #define RTU_XRDC_MDA_W2_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_SA_MASK) 640 641 #define RTU_XRDC_MDA_W2_4_DFMT1_DIDB_MASK (0x100U) 642 #define RTU_XRDC_MDA_W2_4_DFMT1_DIDB_SHIFT (8U) 643 #define RTU_XRDC_MDA_W2_4_DFMT1_DIDB_WIDTH (1U) 644 #define RTU_XRDC_MDA_W2_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_DIDB_MASK) 645 646 #define RTU_XRDC_MDA_W2_4_DFMT1_LPID_MASK (0xF000000U) 647 #define RTU_XRDC_MDA_W2_4_DFMT1_LPID_SHIFT (24U) 648 #define RTU_XRDC_MDA_W2_4_DFMT1_LPID_WIDTH (4U) 649 #define RTU_XRDC_MDA_W2_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_LPID_MASK) 650 651 #define RTU_XRDC_MDA_W2_4_DFMT1_LPE_MASK (0x10000000U) 652 #define RTU_XRDC_MDA_W2_4_DFMT1_LPE_SHIFT (28U) 653 #define RTU_XRDC_MDA_W2_4_DFMT1_LPE_WIDTH (1U) 654 #define RTU_XRDC_MDA_W2_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_LPE_MASK) 655 656 #define RTU_XRDC_MDA_W2_4_DFMT1_DFMT_MASK (0x20000000U) 657 #define RTU_XRDC_MDA_W2_4_DFMT1_DFMT_SHIFT (29U) 658 #define RTU_XRDC_MDA_W2_4_DFMT1_DFMT_WIDTH (1U) 659 #define RTU_XRDC_MDA_W2_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_DFMT_MASK) 660 661 #define RTU_XRDC_MDA_W2_4_DFMT1_LK1_MASK (0x40000000U) 662 #define RTU_XRDC_MDA_W2_4_DFMT1_LK1_SHIFT (30U) 663 #define RTU_XRDC_MDA_W2_4_DFMT1_LK1_WIDTH (1U) 664 #define RTU_XRDC_MDA_W2_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_LK1_MASK) 665 666 #define RTU_XRDC_MDA_W2_4_DFMT1_VLD_MASK (0x80000000U) 667 #define RTU_XRDC_MDA_W2_4_DFMT1_VLD_SHIFT (31U) 668 #define RTU_XRDC_MDA_W2_4_DFMT1_VLD_WIDTH (1U) 669 #define RTU_XRDC_MDA_W2_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_4_DFMT1_VLD_MASK) 670 /*! @} */ 671 672 /*! @name MDA_W3_4_DFMT1 - Master Domain Assignment */ 673 /*! @{ */ 674 675 #define RTU_XRDC_MDA_W3_4_DFMT1_DID_MASK (0xFU) 676 #define RTU_XRDC_MDA_W3_4_DFMT1_DID_SHIFT (0U) 677 #define RTU_XRDC_MDA_W3_4_DFMT1_DID_WIDTH (4U) 678 #define RTU_XRDC_MDA_W3_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_DID_MASK) 679 680 #define RTU_XRDC_MDA_W3_4_DFMT1_PA_MASK (0x30U) 681 #define RTU_XRDC_MDA_W3_4_DFMT1_PA_SHIFT (4U) 682 #define RTU_XRDC_MDA_W3_4_DFMT1_PA_WIDTH (2U) 683 #define RTU_XRDC_MDA_W3_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_PA_MASK) 684 685 #define RTU_XRDC_MDA_W3_4_DFMT1_SA_MASK (0xC0U) 686 #define RTU_XRDC_MDA_W3_4_DFMT1_SA_SHIFT (6U) 687 #define RTU_XRDC_MDA_W3_4_DFMT1_SA_WIDTH (2U) 688 #define RTU_XRDC_MDA_W3_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_SA_MASK) 689 690 #define RTU_XRDC_MDA_W3_4_DFMT1_DIDB_MASK (0x100U) 691 #define RTU_XRDC_MDA_W3_4_DFMT1_DIDB_SHIFT (8U) 692 #define RTU_XRDC_MDA_W3_4_DFMT1_DIDB_WIDTH (1U) 693 #define RTU_XRDC_MDA_W3_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_DIDB_MASK) 694 695 #define RTU_XRDC_MDA_W3_4_DFMT1_LPID_MASK (0xF000000U) 696 #define RTU_XRDC_MDA_W3_4_DFMT1_LPID_SHIFT (24U) 697 #define RTU_XRDC_MDA_W3_4_DFMT1_LPID_WIDTH (4U) 698 #define RTU_XRDC_MDA_W3_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_LPID_MASK) 699 700 #define RTU_XRDC_MDA_W3_4_DFMT1_LPE_MASK (0x10000000U) 701 #define RTU_XRDC_MDA_W3_4_DFMT1_LPE_SHIFT (28U) 702 #define RTU_XRDC_MDA_W3_4_DFMT1_LPE_WIDTH (1U) 703 #define RTU_XRDC_MDA_W3_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_LPE_MASK) 704 705 #define RTU_XRDC_MDA_W3_4_DFMT1_DFMT_MASK (0x20000000U) 706 #define RTU_XRDC_MDA_W3_4_DFMT1_DFMT_SHIFT (29U) 707 #define RTU_XRDC_MDA_W3_4_DFMT1_DFMT_WIDTH (1U) 708 #define RTU_XRDC_MDA_W3_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_DFMT_MASK) 709 710 #define RTU_XRDC_MDA_W3_4_DFMT1_LK1_MASK (0x40000000U) 711 #define RTU_XRDC_MDA_W3_4_DFMT1_LK1_SHIFT (30U) 712 #define RTU_XRDC_MDA_W3_4_DFMT1_LK1_WIDTH (1U) 713 #define RTU_XRDC_MDA_W3_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_LK1_MASK) 714 715 #define RTU_XRDC_MDA_W3_4_DFMT1_VLD_MASK (0x80000000U) 716 #define RTU_XRDC_MDA_W3_4_DFMT1_VLD_SHIFT (31U) 717 #define RTU_XRDC_MDA_W3_4_DFMT1_VLD_WIDTH (1U) 718 #define RTU_XRDC_MDA_W3_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_4_DFMT1_VLD_MASK) 719 /*! @} */ 720 721 /*! @name MDA_W4_4_DFMT1 - Master Domain Assignment */ 722 /*! @{ */ 723 724 #define RTU_XRDC_MDA_W4_4_DFMT1_DID_MASK (0xFU) 725 #define RTU_XRDC_MDA_W4_4_DFMT1_DID_SHIFT (0U) 726 #define RTU_XRDC_MDA_W4_4_DFMT1_DID_WIDTH (4U) 727 #define RTU_XRDC_MDA_W4_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_DID_MASK) 728 729 #define RTU_XRDC_MDA_W4_4_DFMT1_PA_MASK (0x30U) 730 #define RTU_XRDC_MDA_W4_4_DFMT1_PA_SHIFT (4U) 731 #define RTU_XRDC_MDA_W4_4_DFMT1_PA_WIDTH (2U) 732 #define RTU_XRDC_MDA_W4_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_PA_MASK) 733 734 #define RTU_XRDC_MDA_W4_4_DFMT1_SA_MASK (0xC0U) 735 #define RTU_XRDC_MDA_W4_4_DFMT1_SA_SHIFT (6U) 736 #define RTU_XRDC_MDA_W4_4_DFMT1_SA_WIDTH (2U) 737 #define RTU_XRDC_MDA_W4_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_SA_MASK) 738 739 #define RTU_XRDC_MDA_W4_4_DFMT1_DIDB_MASK (0x100U) 740 #define RTU_XRDC_MDA_W4_4_DFMT1_DIDB_SHIFT (8U) 741 #define RTU_XRDC_MDA_W4_4_DFMT1_DIDB_WIDTH (1U) 742 #define RTU_XRDC_MDA_W4_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_DIDB_MASK) 743 744 #define RTU_XRDC_MDA_W4_4_DFMT1_LPID_MASK (0xF000000U) 745 #define RTU_XRDC_MDA_W4_4_DFMT1_LPID_SHIFT (24U) 746 #define RTU_XRDC_MDA_W4_4_DFMT1_LPID_WIDTH (4U) 747 #define RTU_XRDC_MDA_W4_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_LPID_MASK) 748 749 #define RTU_XRDC_MDA_W4_4_DFMT1_LPE_MASK (0x10000000U) 750 #define RTU_XRDC_MDA_W4_4_DFMT1_LPE_SHIFT (28U) 751 #define RTU_XRDC_MDA_W4_4_DFMT1_LPE_WIDTH (1U) 752 #define RTU_XRDC_MDA_W4_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_LPE_MASK) 753 754 #define RTU_XRDC_MDA_W4_4_DFMT1_DFMT_MASK (0x20000000U) 755 #define RTU_XRDC_MDA_W4_4_DFMT1_DFMT_SHIFT (29U) 756 #define RTU_XRDC_MDA_W4_4_DFMT1_DFMT_WIDTH (1U) 757 #define RTU_XRDC_MDA_W4_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_DFMT_MASK) 758 759 #define RTU_XRDC_MDA_W4_4_DFMT1_LK1_MASK (0x40000000U) 760 #define RTU_XRDC_MDA_W4_4_DFMT1_LK1_SHIFT (30U) 761 #define RTU_XRDC_MDA_W4_4_DFMT1_LK1_WIDTH (1U) 762 #define RTU_XRDC_MDA_W4_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_LK1_MASK) 763 764 #define RTU_XRDC_MDA_W4_4_DFMT1_VLD_MASK (0x80000000U) 765 #define RTU_XRDC_MDA_W4_4_DFMT1_VLD_SHIFT (31U) 766 #define RTU_XRDC_MDA_W4_4_DFMT1_VLD_WIDTH (1U) 767 #define RTU_XRDC_MDA_W4_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_4_DFMT1_VLD_MASK) 768 /*! @} */ 769 770 /*! @name MDA_W5_4_DFMT1 - Master Domain Assignment */ 771 /*! @{ */ 772 773 #define RTU_XRDC_MDA_W5_4_DFMT1_DID_MASK (0xFU) 774 #define RTU_XRDC_MDA_W5_4_DFMT1_DID_SHIFT (0U) 775 #define RTU_XRDC_MDA_W5_4_DFMT1_DID_WIDTH (4U) 776 #define RTU_XRDC_MDA_W5_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_DID_MASK) 777 778 #define RTU_XRDC_MDA_W5_4_DFMT1_PA_MASK (0x30U) 779 #define RTU_XRDC_MDA_W5_4_DFMT1_PA_SHIFT (4U) 780 #define RTU_XRDC_MDA_W5_4_DFMT1_PA_WIDTH (2U) 781 #define RTU_XRDC_MDA_W5_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_PA_MASK) 782 783 #define RTU_XRDC_MDA_W5_4_DFMT1_SA_MASK (0xC0U) 784 #define RTU_XRDC_MDA_W5_4_DFMT1_SA_SHIFT (6U) 785 #define RTU_XRDC_MDA_W5_4_DFMT1_SA_WIDTH (2U) 786 #define RTU_XRDC_MDA_W5_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_SA_MASK) 787 788 #define RTU_XRDC_MDA_W5_4_DFMT1_DIDB_MASK (0x100U) 789 #define RTU_XRDC_MDA_W5_4_DFMT1_DIDB_SHIFT (8U) 790 #define RTU_XRDC_MDA_W5_4_DFMT1_DIDB_WIDTH (1U) 791 #define RTU_XRDC_MDA_W5_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_DIDB_MASK) 792 793 #define RTU_XRDC_MDA_W5_4_DFMT1_LPID_MASK (0xF000000U) 794 #define RTU_XRDC_MDA_W5_4_DFMT1_LPID_SHIFT (24U) 795 #define RTU_XRDC_MDA_W5_4_DFMT1_LPID_WIDTH (4U) 796 #define RTU_XRDC_MDA_W5_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_LPID_MASK) 797 798 #define RTU_XRDC_MDA_W5_4_DFMT1_LPE_MASK (0x10000000U) 799 #define RTU_XRDC_MDA_W5_4_DFMT1_LPE_SHIFT (28U) 800 #define RTU_XRDC_MDA_W5_4_DFMT1_LPE_WIDTH (1U) 801 #define RTU_XRDC_MDA_W5_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_LPE_MASK) 802 803 #define RTU_XRDC_MDA_W5_4_DFMT1_DFMT_MASK (0x20000000U) 804 #define RTU_XRDC_MDA_W5_4_DFMT1_DFMT_SHIFT (29U) 805 #define RTU_XRDC_MDA_W5_4_DFMT1_DFMT_WIDTH (1U) 806 #define RTU_XRDC_MDA_W5_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_DFMT_MASK) 807 808 #define RTU_XRDC_MDA_W5_4_DFMT1_LK1_MASK (0x40000000U) 809 #define RTU_XRDC_MDA_W5_4_DFMT1_LK1_SHIFT (30U) 810 #define RTU_XRDC_MDA_W5_4_DFMT1_LK1_WIDTH (1U) 811 #define RTU_XRDC_MDA_W5_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_LK1_MASK) 812 813 #define RTU_XRDC_MDA_W5_4_DFMT1_VLD_MASK (0x80000000U) 814 #define RTU_XRDC_MDA_W5_4_DFMT1_VLD_SHIFT (31U) 815 #define RTU_XRDC_MDA_W5_4_DFMT1_VLD_WIDTH (1U) 816 #define RTU_XRDC_MDA_W5_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_4_DFMT1_VLD_MASK) 817 /*! @} */ 818 819 /*! @name MDA_W6_4_DFMT1 - Master Domain Assignment */ 820 /*! @{ */ 821 822 #define RTU_XRDC_MDA_W6_4_DFMT1_DID_MASK (0xFU) 823 #define RTU_XRDC_MDA_W6_4_DFMT1_DID_SHIFT (0U) 824 #define RTU_XRDC_MDA_W6_4_DFMT1_DID_WIDTH (4U) 825 #define RTU_XRDC_MDA_W6_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_DID_MASK) 826 827 #define RTU_XRDC_MDA_W6_4_DFMT1_PA_MASK (0x30U) 828 #define RTU_XRDC_MDA_W6_4_DFMT1_PA_SHIFT (4U) 829 #define RTU_XRDC_MDA_W6_4_DFMT1_PA_WIDTH (2U) 830 #define RTU_XRDC_MDA_W6_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_PA_MASK) 831 832 #define RTU_XRDC_MDA_W6_4_DFMT1_SA_MASK (0xC0U) 833 #define RTU_XRDC_MDA_W6_4_DFMT1_SA_SHIFT (6U) 834 #define RTU_XRDC_MDA_W6_4_DFMT1_SA_WIDTH (2U) 835 #define RTU_XRDC_MDA_W6_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_SA_MASK) 836 837 #define RTU_XRDC_MDA_W6_4_DFMT1_DIDB_MASK (0x100U) 838 #define RTU_XRDC_MDA_W6_4_DFMT1_DIDB_SHIFT (8U) 839 #define RTU_XRDC_MDA_W6_4_DFMT1_DIDB_WIDTH (1U) 840 #define RTU_XRDC_MDA_W6_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_DIDB_MASK) 841 842 #define RTU_XRDC_MDA_W6_4_DFMT1_LPID_MASK (0xF000000U) 843 #define RTU_XRDC_MDA_W6_4_DFMT1_LPID_SHIFT (24U) 844 #define RTU_XRDC_MDA_W6_4_DFMT1_LPID_WIDTH (4U) 845 #define RTU_XRDC_MDA_W6_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_LPID_MASK) 846 847 #define RTU_XRDC_MDA_W6_4_DFMT1_LPE_MASK (0x10000000U) 848 #define RTU_XRDC_MDA_W6_4_DFMT1_LPE_SHIFT (28U) 849 #define RTU_XRDC_MDA_W6_4_DFMT1_LPE_WIDTH (1U) 850 #define RTU_XRDC_MDA_W6_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_LPE_MASK) 851 852 #define RTU_XRDC_MDA_W6_4_DFMT1_DFMT_MASK (0x20000000U) 853 #define RTU_XRDC_MDA_W6_4_DFMT1_DFMT_SHIFT (29U) 854 #define RTU_XRDC_MDA_W6_4_DFMT1_DFMT_WIDTH (1U) 855 #define RTU_XRDC_MDA_W6_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_DFMT_MASK) 856 857 #define RTU_XRDC_MDA_W6_4_DFMT1_LK1_MASK (0x40000000U) 858 #define RTU_XRDC_MDA_W6_4_DFMT1_LK1_SHIFT (30U) 859 #define RTU_XRDC_MDA_W6_4_DFMT1_LK1_WIDTH (1U) 860 #define RTU_XRDC_MDA_W6_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_LK1_MASK) 861 862 #define RTU_XRDC_MDA_W6_4_DFMT1_VLD_MASK (0x80000000U) 863 #define RTU_XRDC_MDA_W6_4_DFMT1_VLD_SHIFT (31U) 864 #define RTU_XRDC_MDA_W6_4_DFMT1_VLD_WIDTH (1U) 865 #define RTU_XRDC_MDA_W6_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_4_DFMT1_VLD_MASK) 866 /*! @} */ 867 868 /*! @name MDA_W7_4_DFMT1 - Master Domain Assignment */ 869 /*! @{ */ 870 871 #define RTU_XRDC_MDA_W7_4_DFMT1_DID_MASK (0xFU) 872 #define RTU_XRDC_MDA_W7_4_DFMT1_DID_SHIFT (0U) 873 #define RTU_XRDC_MDA_W7_4_DFMT1_DID_WIDTH (4U) 874 #define RTU_XRDC_MDA_W7_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_DID_MASK) 875 876 #define RTU_XRDC_MDA_W7_4_DFMT1_PA_MASK (0x30U) 877 #define RTU_XRDC_MDA_W7_4_DFMT1_PA_SHIFT (4U) 878 #define RTU_XRDC_MDA_W7_4_DFMT1_PA_WIDTH (2U) 879 #define RTU_XRDC_MDA_W7_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_PA_MASK) 880 881 #define RTU_XRDC_MDA_W7_4_DFMT1_SA_MASK (0xC0U) 882 #define RTU_XRDC_MDA_W7_4_DFMT1_SA_SHIFT (6U) 883 #define RTU_XRDC_MDA_W7_4_DFMT1_SA_WIDTH (2U) 884 #define RTU_XRDC_MDA_W7_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_SA_MASK) 885 886 #define RTU_XRDC_MDA_W7_4_DFMT1_DIDB_MASK (0x100U) 887 #define RTU_XRDC_MDA_W7_4_DFMT1_DIDB_SHIFT (8U) 888 #define RTU_XRDC_MDA_W7_4_DFMT1_DIDB_WIDTH (1U) 889 #define RTU_XRDC_MDA_W7_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_DIDB_MASK) 890 891 #define RTU_XRDC_MDA_W7_4_DFMT1_LPID_MASK (0xF000000U) 892 #define RTU_XRDC_MDA_W7_4_DFMT1_LPID_SHIFT (24U) 893 #define RTU_XRDC_MDA_W7_4_DFMT1_LPID_WIDTH (4U) 894 #define RTU_XRDC_MDA_W7_4_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_LPID_MASK) 895 896 #define RTU_XRDC_MDA_W7_4_DFMT1_LPE_MASK (0x10000000U) 897 #define RTU_XRDC_MDA_W7_4_DFMT1_LPE_SHIFT (28U) 898 #define RTU_XRDC_MDA_W7_4_DFMT1_LPE_WIDTH (1U) 899 #define RTU_XRDC_MDA_W7_4_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_LPE_MASK) 900 901 #define RTU_XRDC_MDA_W7_4_DFMT1_DFMT_MASK (0x20000000U) 902 #define RTU_XRDC_MDA_W7_4_DFMT1_DFMT_SHIFT (29U) 903 #define RTU_XRDC_MDA_W7_4_DFMT1_DFMT_WIDTH (1U) 904 #define RTU_XRDC_MDA_W7_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_DFMT_MASK) 905 906 #define RTU_XRDC_MDA_W7_4_DFMT1_LK1_MASK (0x40000000U) 907 #define RTU_XRDC_MDA_W7_4_DFMT1_LK1_SHIFT (30U) 908 #define RTU_XRDC_MDA_W7_4_DFMT1_LK1_WIDTH (1U) 909 #define RTU_XRDC_MDA_W7_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_LK1_MASK) 910 911 #define RTU_XRDC_MDA_W7_4_DFMT1_VLD_MASK (0x80000000U) 912 #define RTU_XRDC_MDA_W7_4_DFMT1_VLD_SHIFT (31U) 913 #define RTU_XRDC_MDA_W7_4_DFMT1_VLD_WIDTH (1U) 914 #define RTU_XRDC_MDA_W7_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_4_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_4_DFMT1_VLD_MASK) 915 /*! @} */ 916 917 /*! @name MDA_W0_5_DFMT1 - Master Domain Assignment */ 918 /*! @{ */ 919 920 #define RTU_XRDC_MDA_W0_5_DFMT1_DID_MASK (0xFU) 921 #define RTU_XRDC_MDA_W0_5_DFMT1_DID_SHIFT (0U) 922 #define RTU_XRDC_MDA_W0_5_DFMT1_DID_WIDTH (4U) 923 #define RTU_XRDC_MDA_W0_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_DID_MASK) 924 925 #define RTU_XRDC_MDA_W0_5_DFMT1_PA_MASK (0x30U) 926 #define RTU_XRDC_MDA_W0_5_DFMT1_PA_SHIFT (4U) 927 #define RTU_XRDC_MDA_W0_5_DFMT1_PA_WIDTH (2U) 928 #define RTU_XRDC_MDA_W0_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_PA_MASK) 929 930 #define RTU_XRDC_MDA_W0_5_DFMT1_SA_MASK (0xC0U) 931 #define RTU_XRDC_MDA_W0_5_DFMT1_SA_SHIFT (6U) 932 #define RTU_XRDC_MDA_W0_5_DFMT1_SA_WIDTH (2U) 933 #define RTU_XRDC_MDA_W0_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_SA_MASK) 934 935 #define RTU_XRDC_MDA_W0_5_DFMT1_DIDB_MASK (0x100U) 936 #define RTU_XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT (8U) 937 #define RTU_XRDC_MDA_W0_5_DFMT1_DIDB_WIDTH (1U) 938 #define RTU_XRDC_MDA_W0_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_DIDB_MASK) 939 940 #define RTU_XRDC_MDA_W0_5_DFMT1_LPID_MASK (0xF000000U) 941 #define RTU_XRDC_MDA_W0_5_DFMT1_LPID_SHIFT (24U) 942 #define RTU_XRDC_MDA_W0_5_DFMT1_LPID_WIDTH (4U) 943 #define RTU_XRDC_MDA_W0_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_LPID_MASK) 944 945 #define RTU_XRDC_MDA_W0_5_DFMT1_LPE_MASK (0x10000000U) 946 #define RTU_XRDC_MDA_W0_5_DFMT1_LPE_SHIFT (28U) 947 #define RTU_XRDC_MDA_W0_5_DFMT1_LPE_WIDTH (1U) 948 #define RTU_XRDC_MDA_W0_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_LPE_MASK) 949 950 #define RTU_XRDC_MDA_W0_5_DFMT1_DFMT_MASK (0x20000000U) 951 #define RTU_XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT (29U) 952 #define RTU_XRDC_MDA_W0_5_DFMT1_DFMT_WIDTH (1U) 953 #define RTU_XRDC_MDA_W0_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_DFMT_MASK) 954 955 #define RTU_XRDC_MDA_W0_5_DFMT1_LK1_MASK (0x40000000U) 956 #define RTU_XRDC_MDA_W0_5_DFMT1_LK1_SHIFT (30U) 957 #define RTU_XRDC_MDA_W0_5_DFMT1_LK1_WIDTH (1U) 958 #define RTU_XRDC_MDA_W0_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_LK1_MASK) 959 960 #define RTU_XRDC_MDA_W0_5_DFMT1_VLD_MASK (0x80000000U) 961 #define RTU_XRDC_MDA_W0_5_DFMT1_VLD_SHIFT (31U) 962 #define RTU_XRDC_MDA_W0_5_DFMT1_VLD_WIDTH (1U) 963 #define RTU_XRDC_MDA_W0_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_5_DFMT1_VLD_MASK) 964 /*! @} */ 965 966 /*! @name MDA_W1_5_DFMT1 - Master Domain Assignment */ 967 /*! @{ */ 968 969 #define RTU_XRDC_MDA_W1_5_DFMT1_DID_MASK (0xFU) 970 #define RTU_XRDC_MDA_W1_5_DFMT1_DID_SHIFT (0U) 971 #define RTU_XRDC_MDA_W1_5_DFMT1_DID_WIDTH (4U) 972 #define RTU_XRDC_MDA_W1_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_DID_MASK) 973 974 #define RTU_XRDC_MDA_W1_5_DFMT1_PA_MASK (0x30U) 975 #define RTU_XRDC_MDA_W1_5_DFMT1_PA_SHIFT (4U) 976 #define RTU_XRDC_MDA_W1_5_DFMT1_PA_WIDTH (2U) 977 #define RTU_XRDC_MDA_W1_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_PA_MASK) 978 979 #define RTU_XRDC_MDA_W1_5_DFMT1_SA_MASK (0xC0U) 980 #define RTU_XRDC_MDA_W1_5_DFMT1_SA_SHIFT (6U) 981 #define RTU_XRDC_MDA_W1_5_DFMT1_SA_WIDTH (2U) 982 #define RTU_XRDC_MDA_W1_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_SA_MASK) 983 984 #define RTU_XRDC_MDA_W1_5_DFMT1_DIDB_MASK (0x100U) 985 #define RTU_XRDC_MDA_W1_5_DFMT1_DIDB_SHIFT (8U) 986 #define RTU_XRDC_MDA_W1_5_DFMT1_DIDB_WIDTH (1U) 987 #define RTU_XRDC_MDA_W1_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_DIDB_MASK) 988 989 #define RTU_XRDC_MDA_W1_5_DFMT1_LPID_MASK (0xF000000U) 990 #define RTU_XRDC_MDA_W1_5_DFMT1_LPID_SHIFT (24U) 991 #define RTU_XRDC_MDA_W1_5_DFMT1_LPID_WIDTH (4U) 992 #define RTU_XRDC_MDA_W1_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_LPID_MASK) 993 994 #define RTU_XRDC_MDA_W1_5_DFMT1_LPE_MASK (0x10000000U) 995 #define RTU_XRDC_MDA_W1_5_DFMT1_LPE_SHIFT (28U) 996 #define RTU_XRDC_MDA_W1_5_DFMT1_LPE_WIDTH (1U) 997 #define RTU_XRDC_MDA_W1_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_LPE_MASK) 998 999 #define RTU_XRDC_MDA_W1_5_DFMT1_DFMT_MASK (0x20000000U) 1000 #define RTU_XRDC_MDA_W1_5_DFMT1_DFMT_SHIFT (29U) 1001 #define RTU_XRDC_MDA_W1_5_DFMT1_DFMT_WIDTH (1U) 1002 #define RTU_XRDC_MDA_W1_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_DFMT_MASK) 1003 1004 #define RTU_XRDC_MDA_W1_5_DFMT1_LK1_MASK (0x40000000U) 1005 #define RTU_XRDC_MDA_W1_5_DFMT1_LK1_SHIFT (30U) 1006 #define RTU_XRDC_MDA_W1_5_DFMT1_LK1_WIDTH (1U) 1007 #define RTU_XRDC_MDA_W1_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_LK1_MASK) 1008 1009 #define RTU_XRDC_MDA_W1_5_DFMT1_VLD_MASK (0x80000000U) 1010 #define RTU_XRDC_MDA_W1_5_DFMT1_VLD_SHIFT (31U) 1011 #define RTU_XRDC_MDA_W1_5_DFMT1_VLD_WIDTH (1U) 1012 #define RTU_XRDC_MDA_W1_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_5_DFMT1_VLD_MASK) 1013 /*! @} */ 1014 1015 /*! @name MDA_W2_5_DFMT1 - Master Domain Assignment */ 1016 /*! @{ */ 1017 1018 #define RTU_XRDC_MDA_W2_5_DFMT1_DID_MASK (0xFU) 1019 #define RTU_XRDC_MDA_W2_5_DFMT1_DID_SHIFT (0U) 1020 #define RTU_XRDC_MDA_W2_5_DFMT1_DID_WIDTH (4U) 1021 #define RTU_XRDC_MDA_W2_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_DID_MASK) 1022 1023 #define RTU_XRDC_MDA_W2_5_DFMT1_PA_MASK (0x30U) 1024 #define RTU_XRDC_MDA_W2_5_DFMT1_PA_SHIFT (4U) 1025 #define RTU_XRDC_MDA_W2_5_DFMT1_PA_WIDTH (2U) 1026 #define RTU_XRDC_MDA_W2_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_PA_MASK) 1027 1028 #define RTU_XRDC_MDA_W2_5_DFMT1_SA_MASK (0xC0U) 1029 #define RTU_XRDC_MDA_W2_5_DFMT1_SA_SHIFT (6U) 1030 #define RTU_XRDC_MDA_W2_5_DFMT1_SA_WIDTH (2U) 1031 #define RTU_XRDC_MDA_W2_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_SA_MASK) 1032 1033 #define RTU_XRDC_MDA_W2_5_DFMT1_DIDB_MASK (0x100U) 1034 #define RTU_XRDC_MDA_W2_5_DFMT1_DIDB_SHIFT (8U) 1035 #define RTU_XRDC_MDA_W2_5_DFMT1_DIDB_WIDTH (1U) 1036 #define RTU_XRDC_MDA_W2_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_DIDB_MASK) 1037 1038 #define RTU_XRDC_MDA_W2_5_DFMT1_LPID_MASK (0xF000000U) 1039 #define RTU_XRDC_MDA_W2_5_DFMT1_LPID_SHIFT (24U) 1040 #define RTU_XRDC_MDA_W2_5_DFMT1_LPID_WIDTH (4U) 1041 #define RTU_XRDC_MDA_W2_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_LPID_MASK) 1042 1043 #define RTU_XRDC_MDA_W2_5_DFMT1_LPE_MASK (0x10000000U) 1044 #define RTU_XRDC_MDA_W2_5_DFMT1_LPE_SHIFT (28U) 1045 #define RTU_XRDC_MDA_W2_5_DFMT1_LPE_WIDTH (1U) 1046 #define RTU_XRDC_MDA_W2_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_LPE_MASK) 1047 1048 #define RTU_XRDC_MDA_W2_5_DFMT1_DFMT_MASK (0x20000000U) 1049 #define RTU_XRDC_MDA_W2_5_DFMT1_DFMT_SHIFT (29U) 1050 #define RTU_XRDC_MDA_W2_5_DFMT1_DFMT_WIDTH (1U) 1051 #define RTU_XRDC_MDA_W2_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_DFMT_MASK) 1052 1053 #define RTU_XRDC_MDA_W2_5_DFMT1_LK1_MASK (0x40000000U) 1054 #define RTU_XRDC_MDA_W2_5_DFMT1_LK1_SHIFT (30U) 1055 #define RTU_XRDC_MDA_W2_5_DFMT1_LK1_WIDTH (1U) 1056 #define RTU_XRDC_MDA_W2_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_LK1_MASK) 1057 1058 #define RTU_XRDC_MDA_W2_5_DFMT1_VLD_MASK (0x80000000U) 1059 #define RTU_XRDC_MDA_W2_5_DFMT1_VLD_SHIFT (31U) 1060 #define RTU_XRDC_MDA_W2_5_DFMT1_VLD_WIDTH (1U) 1061 #define RTU_XRDC_MDA_W2_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_5_DFMT1_VLD_MASK) 1062 /*! @} */ 1063 1064 /*! @name MDA_W3_5_DFMT1 - Master Domain Assignment */ 1065 /*! @{ */ 1066 1067 #define RTU_XRDC_MDA_W3_5_DFMT1_DID_MASK (0xFU) 1068 #define RTU_XRDC_MDA_W3_5_DFMT1_DID_SHIFT (0U) 1069 #define RTU_XRDC_MDA_W3_5_DFMT1_DID_WIDTH (4U) 1070 #define RTU_XRDC_MDA_W3_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_DID_MASK) 1071 1072 #define RTU_XRDC_MDA_W3_5_DFMT1_PA_MASK (0x30U) 1073 #define RTU_XRDC_MDA_W3_5_DFMT1_PA_SHIFT (4U) 1074 #define RTU_XRDC_MDA_W3_5_DFMT1_PA_WIDTH (2U) 1075 #define RTU_XRDC_MDA_W3_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_PA_MASK) 1076 1077 #define RTU_XRDC_MDA_W3_5_DFMT1_SA_MASK (0xC0U) 1078 #define RTU_XRDC_MDA_W3_5_DFMT1_SA_SHIFT (6U) 1079 #define RTU_XRDC_MDA_W3_5_DFMT1_SA_WIDTH (2U) 1080 #define RTU_XRDC_MDA_W3_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_SA_MASK) 1081 1082 #define RTU_XRDC_MDA_W3_5_DFMT1_DIDB_MASK (0x100U) 1083 #define RTU_XRDC_MDA_W3_5_DFMT1_DIDB_SHIFT (8U) 1084 #define RTU_XRDC_MDA_W3_5_DFMT1_DIDB_WIDTH (1U) 1085 #define RTU_XRDC_MDA_W3_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_DIDB_MASK) 1086 1087 #define RTU_XRDC_MDA_W3_5_DFMT1_LPID_MASK (0xF000000U) 1088 #define RTU_XRDC_MDA_W3_5_DFMT1_LPID_SHIFT (24U) 1089 #define RTU_XRDC_MDA_W3_5_DFMT1_LPID_WIDTH (4U) 1090 #define RTU_XRDC_MDA_W3_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_LPID_MASK) 1091 1092 #define RTU_XRDC_MDA_W3_5_DFMT1_LPE_MASK (0x10000000U) 1093 #define RTU_XRDC_MDA_W3_5_DFMT1_LPE_SHIFT (28U) 1094 #define RTU_XRDC_MDA_W3_5_DFMT1_LPE_WIDTH (1U) 1095 #define RTU_XRDC_MDA_W3_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_LPE_MASK) 1096 1097 #define RTU_XRDC_MDA_W3_5_DFMT1_DFMT_MASK (0x20000000U) 1098 #define RTU_XRDC_MDA_W3_5_DFMT1_DFMT_SHIFT (29U) 1099 #define RTU_XRDC_MDA_W3_5_DFMT1_DFMT_WIDTH (1U) 1100 #define RTU_XRDC_MDA_W3_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_DFMT_MASK) 1101 1102 #define RTU_XRDC_MDA_W3_5_DFMT1_LK1_MASK (0x40000000U) 1103 #define RTU_XRDC_MDA_W3_5_DFMT1_LK1_SHIFT (30U) 1104 #define RTU_XRDC_MDA_W3_5_DFMT1_LK1_WIDTH (1U) 1105 #define RTU_XRDC_MDA_W3_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_LK1_MASK) 1106 1107 #define RTU_XRDC_MDA_W3_5_DFMT1_VLD_MASK (0x80000000U) 1108 #define RTU_XRDC_MDA_W3_5_DFMT1_VLD_SHIFT (31U) 1109 #define RTU_XRDC_MDA_W3_5_DFMT1_VLD_WIDTH (1U) 1110 #define RTU_XRDC_MDA_W3_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_5_DFMT1_VLD_MASK) 1111 /*! @} */ 1112 1113 /*! @name MDA_W4_5_DFMT1 - Master Domain Assignment */ 1114 /*! @{ */ 1115 1116 #define RTU_XRDC_MDA_W4_5_DFMT1_DID_MASK (0xFU) 1117 #define RTU_XRDC_MDA_W4_5_DFMT1_DID_SHIFT (0U) 1118 #define RTU_XRDC_MDA_W4_5_DFMT1_DID_WIDTH (4U) 1119 #define RTU_XRDC_MDA_W4_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_DID_MASK) 1120 1121 #define RTU_XRDC_MDA_W4_5_DFMT1_PA_MASK (0x30U) 1122 #define RTU_XRDC_MDA_W4_5_DFMT1_PA_SHIFT (4U) 1123 #define RTU_XRDC_MDA_W4_5_DFMT1_PA_WIDTH (2U) 1124 #define RTU_XRDC_MDA_W4_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_PA_MASK) 1125 1126 #define RTU_XRDC_MDA_W4_5_DFMT1_SA_MASK (0xC0U) 1127 #define RTU_XRDC_MDA_W4_5_DFMT1_SA_SHIFT (6U) 1128 #define RTU_XRDC_MDA_W4_5_DFMT1_SA_WIDTH (2U) 1129 #define RTU_XRDC_MDA_W4_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_SA_MASK) 1130 1131 #define RTU_XRDC_MDA_W4_5_DFMT1_DIDB_MASK (0x100U) 1132 #define RTU_XRDC_MDA_W4_5_DFMT1_DIDB_SHIFT (8U) 1133 #define RTU_XRDC_MDA_W4_5_DFMT1_DIDB_WIDTH (1U) 1134 #define RTU_XRDC_MDA_W4_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_DIDB_MASK) 1135 1136 #define RTU_XRDC_MDA_W4_5_DFMT1_LPID_MASK (0xF000000U) 1137 #define RTU_XRDC_MDA_W4_5_DFMT1_LPID_SHIFT (24U) 1138 #define RTU_XRDC_MDA_W4_5_DFMT1_LPID_WIDTH (4U) 1139 #define RTU_XRDC_MDA_W4_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_LPID_MASK) 1140 1141 #define RTU_XRDC_MDA_W4_5_DFMT1_LPE_MASK (0x10000000U) 1142 #define RTU_XRDC_MDA_W4_5_DFMT1_LPE_SHIFT (28U) 1143 #define RTU_XRDC_MDA_W4_5_DFMT1_LPE_WIDTH (1U) 1144 #define RTU_XRDC_MDA_W4_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_LPE_MASK) 1145 1146 #define RTU_XRDC_MDA_W4_5_DFMT1_DFMT_MASK (0x20000000U) 1147 #define RTU_XRDC_MDA_W4_5_DFMT1_DFMT_SHIFT (29U) 1148 #define RTU_XRDC_MDA_W4_5_DFMT1_DFMT_WIDTH (1U) 1149 #define RTU_XRDC_MDA_W4_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_DFMT_MASK) 1150 1151 #define RTU_XRDC_MDA_W4_5_DFMT1_LK1_MASK (0x40000000U) 1152 #define RTU_XRDC_MDA_W4_5_DFMT1_LK1_SHIFT (30U) 1153 #define RTU_XRDC_MDA_W4_5_DFMT1_LK1_WIDTH (1U) 1154 #define RTU_XRDC_MDA_W4_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_LK1_MASK) 1155 1156 #define RTU_XRDC_MDA_W4_5_DFMT1_VLD_MASK (0x80000000U) 1157 #define RTU_XRDC_MDA_W4_5_DFMT1_VLD_SHIFT (31U) 1158 #define RTU_XRDC_MDA_W4_5_DFMT1_VLD_WIDTH (1U) 1159 #define RTU_XRDC_MDA_W4_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_5_DFMT1_VLD_MASK) 1160 /*! @} */ 1161 1162 /*! @name MDA_W5_5_DFMT1 - Master Domain Assignment */ 1163 /*! @{ */ 1164 1165 #define RTU_XRDC_MDA_W5_5_DFMT1_DID_MASK (0xFU) 1166 #define RTU_XRDC_MDA_W5_5_DFMT1_DID_SHIFT (0U) 1167 #define RTU_XRDC_MDA_W5_5_DFMT1_DID_WIDTH (4U) 1168 #define RTU_XRDC_MDA_W5_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_DID_MASK) 1169 1170 #define RTU_XRDC_MDA_W5_5_DFMT1_PA_MASK (0x30U) 1171 #define RTU_XRDC_MDA_W5_5_DFMT1_PA_SHIFT (4U) 1172 #define RTU_XRDC_MDA_W5_5_DFMT1_PA_WIDTH (2U) 1173 #define RTU_XRDC_MDA_W5_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_PA_MASK) 1174 1175 #define RTU_XRDC_MDA_W5_5_DFMT1_SA_MASK (0xC0U) 1176 #define RTU_XRDC_MDA_W5_5_DFMT1_SA_SHIFT (6U) 1177 #define RTU_XRDC_MDA_W5_5_DFMT1_SA_WIDTH (2U) 1178 #define RTU_XRDC_MDA_W5_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_SA_MASK) 1179 1180 #define RTU_XRDC_MDA_W5_5_DFMT1_DIDB_MASK (0x100U) 1181 #define RTU_XRDC_MDA_W5_5_DFMT1_DIDB_SHIFT (8U) 1182 #define RTU_XRDC_MDA_W5_5_DFMT1_DIDB_WIDTH (1U) 1183 #define RTU_XRDC_MDA_W5_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_DIDB_MASK) 1184 1185 #define RTU_XRDC_MDA_W5_5_DFMT1_LPID_MASK (0xF000000U) 1186 #define RTU_XRDC_MDA_W5_5_DFMT1_LPID_SHIFT (24U) 1187 #define RTU_XRDC_MDA_W5_5_DFMT1_LPID_WIDTH (4U) 1188 #define RTU_XRDC_MDA_W5_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_LPID_MASK) 1189 1190 #define RTU_XRDC_MDA_W5_5_DFMT1_LPE_MASK (0x10000000U) 1191 #define RTU_XRDC_MDA_W5_5_DFMT1_LPE_SHIFT (28U) 1192 #define RTU_XRDC_MDA_W5_5_DFMT1_LPE_WIDTH (1U) 1193 #define RTU_XRDC_MDA_W5_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_LPE_MASK) 1194 1195 #define RTU_XRDC_MDA_W5_5_DFMT1_DFMT_MASK (0x20000000U) 1196 #define RTU_XRDC_MDA_W5_5_DFMT1_DFMT_SHIFT (29U) 1197 #define RTU_XRDC_MDA_W5_5_DFMT1_DFMT_WIDTH (1U) 1198 #define RTU_XRDC_MDA_W5_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_DFMT_MASK) 1199 1200 #define RTU_XRDC_MDA_W5_5_DFMT1_LK1_MASK (0x40000000U) 1201 #define RTU_XRDC_MDA_W5_5_DFMT1_LK1_SHIFT (30U) 1202 #define RTU_XRDC_MDA_W5_5_DFMT1_LK1_WIDTH (1U) 1203 #define RTU_XRDC_MDA_W5_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_LK1_MASK) 1204 1205 #define RTU_XRDC_MDA_W5_5_DFMT1_VLD_MASK (0x80000000U) 1206 #define RTU_XRDC_MDA_W5_5_DFMT1_VLD_SHIFT (31U) 1207 #define RTU_XRDC_MDA_W5_5_DFMT1_VLD_WIDTH (1U) 1208 #define RTU_XRDC_MDA_W5_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_5_DFMT1_VLD_MASK) 1209 /*! @} */ 1210 1211 /*! @name MDA_W6_5_DFMT1 - Master Domain Assignment */ 1212 /*! @{ */ 1213 1214 #define RTU_XRDC_MDA_W6_5_DFMT1_DID_MASK (0xFU) 1215 #define RTU_XRDC_MDA_W6_5_DFMT1_DID_SHIFT (0U) 1216 #define RTU_XRDC_MDA_W6_5_DFMT1_DID_WIDTH (4U) 1217 #define RTU_XRDC_MDA_W6_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_DID_MASK) 1218 1219 #define RTU_XRDC_MDA_W6_5_DFMT1_PA_MASK (0x30U) 1220 #define RTU_XRDC_MDA_W6_5_DFMT1_PA_SHIFT (4U) 1221 #define RTU_XRDC_MDA_W6_5_DFMT1_PA_WIDTH (2U) 1222 #define RTU_XRDC_MDA_W6_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_PA_MASK) 1223 1224 #define RTU_XRDC_MDA_W6_5_DFMT1_SA_MASK (0xC0U) 1225 #define RTU_XRDC_MDA_W6_5_DFMT1_SA_SHIFT (6U) 1226 #define RTU_XRDC_MDA_W6_5_DFMT1_SA_WIDTH (2U) 1227 #define RTU_XRDC_MDA_W6_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_SA_MASK) 1228 1229 #define RTU_XRDC_MDA_W6_5_DFMT1_DIDB_MASK (0x100U) 1230 #define RTU_XRDC_MDA_W6_5_DFMT1_DIDB_SHIFT (8U) 1231 #define RTU_XRDC_MDA_W6_5_DFMT1_DIDB_WIDTH (1U) 1232 #define RTU_XRDC_MDA_W6_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_DIDB_MASK) 1233 1234 #define RTU_XRDC_MDA_W6_5_DFMT1_LPID_MASK (0xF000000U) 1235 #define RTU_XRDC_MDA_W6_5_DFMT1_LPID_SHIFT (24U) 1236 #define RTU_XRDC_MDA_W6_5_DFMT1_LPID_WIDTH (4U) 1237 #define RTU_XRDC_MDA_W6_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_LPID_MASK) 1238 1239 #define RTU_XRDC_MDA_W6_5_DFMT1_LPE_MASK (0x10000000U) 1240 #define RTU_XRDC_MDA_W6_5_DFMT1_LPE_SHIFT (28U) 1241 #define RTU_XRDC_MDA_W6_5_DFMT1_LPE_WIDTH (1U) 1242 #define RTU_XRDC_MDA_W6_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_LPE_MASK) 1243 1244 #define RTU_XRDC_MDA_W6_5_DFMT1_DFMT_MASK (0x20000000U) 1245 #define RTU_XRDC_MDA_W6_5_DFMT1_DFMT_SHIFT (29U) 1246 #define RTU_XRDC_MDA_W6_5_DFMT1_DFMT_WIDTH (1U) 1247 #define RTU_XRDC_MDA_W6_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_DFMT_MASK) 1248 1249 #define RTU_XRDC_MDA_W6_5_DFMT1_LK1_MASK (0x40000000U) 1250 #define RTU_XRDC_MDA_W6_5_DFMT1_LK1_SHIFT (30U) 1251 #define RTU_XRDC_MDA_W6_5_DFMT1_LK1_WIDTH (1U) 1252 #define RTU_XRDC_MDA_W6_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_LK1_MASK) 1253 1254 #define RTU_XRDC_MDA_W6_5_DFMT1_VLD_MASK (0x80000000U) 1255 #define RTU_XRDC_MDA_W6_5_DFMT1_VLD_SHIFT (31U) 1256 #define RTU_XRDC_MDA_W6_5_DFMT1_VLD_WIDTH (1U) 1257 #define RTU_XRDC_MDA_W6_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_5_DFMT1_VLD_MASK) 1258 /*! @} */ 1259 1260 /*! @name MDA_W7_5_DFMT1 - Master Domain Assignment */ 1261 /*! @{ */ 1262 1263 #define RTU_XRDC_MDA_W7_5_DFMT1_DID_MASK (0xFU) 1264 #define RTU_XRDC_MDA_W7_5_DFMT1_DID_SHIFT (0U) 1265 #define RTU_XRDC_MDA_W7_5_DFMT1_DID_WIDTH (4U) 1266 #define RTU_XRDC_MDA_W7_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_DID_MASK) 1267 1268 #define RTU_XRDC_MDA_W7_5_DFMT1_PA_MASK (0x30U) 1269 #define RTU_XRDC_MDA_W7_5_DFMT1_PA_SHIFT (4U) 1270 #define RTU_XRDC_MDA_W7_5_DFMT1_PA_WIDTH (2U) 1271 #define RTU_XRDC_MDA_W7_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_PA_MASK) 1272 1273 #define RTU_XRDC_MDA_W7_5_DFMT1_SA_MASK (0xC0U) 1274 #define RTU_XRDC_MDA_W7_5_DFMT1_SA_SHIFT (6U) 1275 #define RTU_XRDC_MDA_W7_5_DFMT1_SA_WIDTH (2U) 1276 #define RTU_XRDC_MDA_W7_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_SA_MASK) 1277 1278 #define RTU_XRDC_MDA_W7_5_DFMT1_DIDB_MASK (0x100U) 1279 #define RTU_XRDC_MDA_W7_5_DFMT1_DIDB_SHIFT (8U) 1280 #define RTU_XRDC_MDA_W7_5_DFMT1_DIDB_WIDTH (1U) 1281 #define RTU_XRDC_MDA_W7_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_DIDB_MASK) 1282 1283 #define RTU_XRDC_MDA_W7_5_DFMT1_LPID_MASK (0xF000000U) 1284 #define RTU_XRDC_MDA_W7_5_DFMT1_LPID_SHIFT (24U) 1285 #define RTU_XRDC_MDA_W7_5_DFMT1_LPID_WIDTH (4U) 1286 #define RTU_XRDC_MDA_W7_5_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_LPID_MASK) 1287 1288 #define RTU_XRDC_MDA_W7_5_DFMT1_LPE_MASK (0x10000000U) 1289 #define RTU_XRDC_MDA_W7_5_DFMT1_LPE_SHIFT (28U) 1290 #define RTU_XRDC_MDA_W7_5_DFMT1_LPE_WIDTH (1U) 1291 #define RTU_XRDC_MDA_W7_5_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_LPE_MASK) 1292 1293 #define RTU_XRDC_MDA_W7_5_DFMT1_DFMT_MASK (0x20000000U) 1294 #define RTU_XRDC_MDA_W7_5_DFMT1_DFMT_SHIFT (29U) 1295 #define RTU_XRDC_MDA_W7_5_DFMT1_DFMT_WIDTH (1U) 1296 #define RTU_XRDC_MDA_W7_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_DFMT_MASK) 1297 1298 #define RTU_XRDC_MDA_W7_5_DFMT1_LK1_MASK (0x40000000U) 1299 #define RTU_XRDC_MDA_W7_5_DFMT1_LK1_SHIFT (30U) 1300 #define RTU_XRDC_MDA_W7_5_DFMT1_LK1_WIDTH (1U) 1301 #define RTU_XRDC_MDA_W7_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_LK1_MASK) 1302 1303 #define RTU_XRDC_MDA_W7_5_DFMT1_VLD_MASK (0x80000000U) 1304 #define RTU_XRDC_MDA_W7_5_DFMT1_VLD_SHIFT (31U) 1305 #define RTU_XRDC_MDA_W7_5_DFMT1_VLD_WIDTH (1U) 1306 #define RTU_XRDC_MDA_W7_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_5_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_5_DFMT1_VLD_MASK) 1307 /*! @} */ 1308 1309 /*! @name MDA_W0_6_DFMT1 - Master Domain Assignment */ 1310 /*! @{ */ 1311 1312 #define RTU_XRDC_MDA_W0_6_DFMT1_DID_MASK (0xFU) 1313 #define RTU_XRDC_MDA_W0_6_DFMT1_DID_SHIFT (0U) 1314 #define RTU_XRDC_MDA_W0_6_DFMT1_DID_WIDTH (4U) 1315 #define RTU_XRDC_MDA_W0_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_DID_MASK) 1316 1317 #define RTU_XRDC_MDA_W0_6_DFMT1_PA_MASK (0x30U) 1318 #define RTU_XRDC_MDA_W0_6_DFMT1_PA_SHIFT (4U) 1319 #define RTU_XRDC_MDA_W0_6_DFMT1_PA_WIDTH (2U) 1320 #define RTU_XRDC_MDA_W0_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_PA_MASK) 1321 1322 #define RTU_XRDC_MDA_W0_6_DFMT1_SA_MASK (0xC0U) 1323 #define RTU_XRDC_MDA_W0_6_DFMT1_SA_SHIFT (6U) 1324 #define RTU_XRDC_MDA_W0_6_DFMT1_SA_WIDTH (2U) 1325 #define RTU_XRDC_MDA_W0_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_SA_MASK) 1326 1327 #define RTU_XRDC_MDA_W0_6_DFMT1_DIDB_MASK (0x100U) 1328 #define RTU_XRDC_MDA_W0_6_DFMT1_DIDB_SHIFT (8U) 1329 #define RTU_XRDC_MDA_W0_6_DFMT1_DIDB_WIDTH (1U) 1330 #define RTU_XRDC_MDA_W0_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_DIDB_MASK) 1331 1332 #define RTU_XRDC_MDA_W0_6_DFMT1_LPID_MASK (0xF000000U) 1333 #define RTU_XRDC_MDA_W0_6_DFMT1_LPID_SHIFT (24U) 1334 #define RTU_XRDC_MDA_W0_6_DFMT1_LPID_WIDTH (4U) 1335 #define RTU_XRDC_MDA_W0_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_LPID_MASK) 1336 1337 #define RTU_XRDC_MDA_W0_6_DFMT1_LPE_MASK (0x10000000U) 1338 #define RTU_XRDC_MDA_W0_6_DFMT1_LPE_SHIFT (28U) 1339 #define RTU_XRDC_MDA_W0_6_DFMT1_LPE_WIDTH (1U) 1340 #define RTU_XRDC_MDA_W0_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_LPE_MASK) 1341 1342 #define RTU_XRDC_MDA_W0_6_DFMT1_DFMT_MASK (0x20000000U) 1343 #define RTU_XRDC_MDA_W0_6_DFMT1_DFMT_SHIFT (29U) 1344 #define RTU_XRDC_MDA_W0_6_DFMT1_DFMT_WIDTH (1U) 1345 #define RTU_XRDC_MDA_W0_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_DFMT_MASK) 1346 1347 #define RTU_XRDC_MDA_W0_6_DFMT1_LK1_MASK (0x40000000U) 1348 #define RTU_XRDC_MDA_W0_6_DFMT1_LK1_SHIFT (30U) 1349 #define RTU_XRDC_MDA_W0_6_DFMT1_LK1_WIDTH (1U) 1350 #define RTU_XRDC_MDA_W0_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_LK1_MASK) 1351 1352 #define RTU_XRDC_MDA_W0_6_DFMT1_VLD_MASK (0x80000000U) 1353 #define RTU_XRDC_MDA_W0_6_DFMT1_VLD_SHIFT (31U) 1354 #define RTU_XRDC_MDA_W0_6_DFMT1_VLD_WIDTH (1U) 1355 #define RTU_XRDC_MDA_W0_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_6_DFMT1_VLD_MASK) 1356 /*! @} */ 1357 1358 /*! @name MDA_W1_6_DFMT1 - Master Domain Assignment */ 1359 /*! @{ */ 1360 1361 #define RTU_XRDC_MDA_W1_6_DFMT1_DID_MASK (0xFU) 1362 #define RTU_XRDC_MDA_W1_6_DFMT1_DID_SHIFT (0U) 1363 #define RTU_XRDC_MDA_W1_6_DFMT1_DID_WIDTH (4U) 1364 #define RTU_XRDC_MDA_W1_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_DID_MASK) 1365 1366 #define RTU_XRDC_MDA_W1_6_DFMT1_PA_MASK (0x30U) 1367 #define RTU_XRDC_MDA_W1_6_DFMT1_PA_SHIFT (4U) 1368 #define RTU_XRDC_MDA_W1_6_DFMT1_PA_WIDTH (2U) 1369 #define RTU_XRDC_MDA_W1_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_PA_MASK) 1370 1371 #define RTU_XRDC_MDA_W1_6_DFMT1_SA_MASK (0xC0U) 1372 #define RTU_XRDC_MDA_W1_6_DFMT1_SA_SHIFT (6U) 1373 #define RTU_XRDC_MDA_W1_6_DFMT1_SA_WIDTH (2U) 1374 #define RTU_XRDC_MDA_W1_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_SA_MASK) 1375 1376 #define RTU_XRDC_MDA_W1_6_DFMT1_DIDB_MASK (0x100U) 1377 #define RTU_XRDC_MDA_W1_6_DFMT1_DIDB_SHIFT (8U) 1378 #define RTU_XRDC_MDA_W1_6_DFMT1_DIDB_WIDTH (1U) 1379 #define RTU_XRDC_MDA_W1_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_DIDB_MASK) 1380 1381 #define RTU_XRDC_MDA_W1_6_DFMT1_LPID_MASK (0xF000000U) 1382 #define RTU_XRDC_MDA_W1_6_DFMT1_LPID_SHIFT (24U) 1383 #define RTU_XRDC_MDA_W1_6_DFMT1_LPID_WIDTH (4U) 1384 #define RTU_XRDC_MDA_W1_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_LPID_MASK) 1385 1386 #define RTU_XRDC_MDA_W1_6_DFMT1_LPE_MASK (0x10000000U) 1387 #define RTU_XRDC_MDA_W1_6_DFMT1_LPE_SHIFT (28U) 1388 #define RTU_XRDC_MDA_W1_6_DFMT1_LPE_WIDTH (1U) 1389 #define RTU_XRDC_MDA_W1_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_LPE_MASK) 1390 1391 #define RTU_XRDC_MDA_W1_6_DFMT1_DFMT_MASK (0x20000000U) 1392 #define RTU_XRDC_MDA_W1_6_DFMT1_DFMT_SHIFT (29U) 1393 #define RTU_XRDC_MDA_W1_6_DFMT1_DFMT_WIDTH (1U) 1394 #define RTU_XRDC_MDA_W1_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_DFMT_MASK) 1395 1396 #define RTU_XRDC_MDA_W1_6_DFMT1_LK1_MASK (0x40000000U) 1397 #define RTU_XRDC_MDA_W1_6_DFMT1_LK1_SHIFT (30U) 1398 #define RTU_XRDC_MDA_W1_6_DFMT1_LK1_WIDTH (1U) 1399 #define RTU_XRDC_MDA_W1_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_LK1_MASK) 1400 1401 #define RTU_XRDC_MDA_W1_6_DFMT1_VLD_MASK (0x80000000U) 1402 #define RTU_XRDC_MDA_W1_6_DFMT1_VLD_SHIFT (31U) 1403 #define RTU_XRDC_MDA_W1_6_DFMT1_VLD_WIDTH (1U) 1404 #define RTU_XRDC_MDA_W1_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_6_DFMT1_VLD_MASK) 1405 /*! @} */ 1406 1407 /*! @name MDA_W2_6_DFMT1 - Master Domain Assignment */ 1408 /*! @{ */ 1409 1410 #define RTU_XRDC_MDA_W2_6_DFMT1_DID_MASK (0xFU) 1411 #define RTU_XRDC_MDA_W2_6_DFMT1_DID_SHIFT (0U) 1412 #define RTU_XRDC_MDA_W2_6_DFMT1_DID_WIDTH (4U) 1413 #define RTU_XRDC_MDA_W2_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_DID_MASK) 1414 1415 #define RTU_XRDC_MDA_W2_6_DFMT1_PA_MASK (0x30U) 1416 #define RTU_XRDC_MDA_W2_6_DFMT1_PA_SHIFT (4U) 1417 #define RTU_XRDC_MDA_W2_6_DFMT1_PA_WIDTH (2U) 1418 #define RTU_XRDC_MDA_W2_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_PA_MASK) 1419 1420 #define RTU_XRDC_MDA_W2_6_DFMT1_SA_MASK (0xC0U) 1421 #define RTU_XRDC_MDA_W2_6_DFMT1_SA_SHIFT (6U) 1422 #define RTU_XRDC_MDA_W2_6_DFMT1_SA_WIDTH (2U) 1423 #define RTU_XRDC_MDA_W2_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_SA_MASK) 1424 1425 #define RTU_XRDC_MDA_W2_6_DFMT1_DIDB_MASK (0x100U) 1426 #define RTU_XRDC_MDA_W2_6_DFMT1_DIDB_SHIFT (8U) 1427 #define RTU_XRDC_MDA_W2_6_DFMT1_DIDB_WIDTH (1U) 1428 #define RTU_XRDC_MDA_W2_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_DIDB_MASK) 1429 1430 #define RTU_XRDC_MDA_W2_6_DFMT1_LPID_MASK (0xF000000U) 1431 #define RTU_XRDC_MDA_W2_6_DFMT1_LPID_SHIFT (24U) 1432 #define RTU_XRDC_MDA_W2_6_DFMT1_LPID_WIDTH (4U) 1433 #define RTU_XRDC_MDA_W2_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_LPID_MASK) 1434 1435 #define RTU_XRDC_MDA_W2_6_DFMT1_LPE_MASK (0x10000000U) 1436 #define RTU_XRDC_MDA_W2_6_DFMT1_LPE_SHIFT (28U) 1437 #define RTU_XRDC_MDA_W2_6_DFMT1_LPE_WIDTH (1U) 1438 #define RTU_XRDC_MDA_W2_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_LPE_MASK) 1439 1440 #define RTU_XRDC_MDA_W2_6_DFMT1_DFMT_MASK (0x20000000U) 1441 #define RTU_XRDC_MDA_W2_6_DFMT1_DFMT_SHIFT (29U) 1442 #define RTU_XRDC_MDA_W2_6_DFMT1_DFMT_WIDTH (1U) 1443 #define RTU_XRDC_MDA_W2_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_DFMT_MASK) 1444 1445 #define RTU_XRDC_MDA_W2_6_DFMT1_LK1_MASK (0x40000000U) 1446 #define RTU_XRDC_MDA_W2_6_DFMT1_LK1_SHIFT (30U) 1447 #define RTU_XRDC_MDA_W2_6_DFMT1_LK1_WIDTH (1U) 1448 #define RTU_XRDC_MDA_W2_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_LK1_MASK) 1449 1450 #define RTU_XRDC_MDA_W2_6_DFMT1_VLD_MASK (0x80000000U) 1451 #define RTU_XRDC_MDA_W2_6_DFMT1_VLD_SHIFT (31U) 1452 #define RTU_XRDC_MDA_W2_6_DFMT1_VLD_WIDTH (1U) 1453 #define RTU_XRDC_MDA_W2_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_6_DFMT1_VLD_MASK) 1454 /*! @} */ 1455 1456 /*! @name MDA_W3_6_DFMT1 - Master Domain Assignment */ 1457 /*! @{ */ 1458 1459 #define RTU_XRDC_MDA_W3_6_DFMT1_DID_MASK (0xFU) 1460 #define RTU_XRDC_MDA_W3_6_DFMT1_DID_SHIFT (0U) 1461 #define RTU_XRDC_MDA_W3_6_DFMT1_DID_WIDTH (4U) 1462 #define RTU_XRDC_MDA_W3_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_DID_MASK) 1463 1464 #define RTU_XRDC_MDA_W3_6_DFMT1_PA_MASK (0x30U) 1465 #define RTU_XRDC_MDA_W3_6_DFMT1_PA_SHIFT (4U) 1466 #define RTU_XRDC_MDA_W3_6_DFMT1_PA_WIDTH (2U) 1467 #define RTU_XRDC_MDA_W3_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_PA_MASK) 1468 1469 #define RTU_XRDC_MDA_W3_6_DFMT1_SA_MASK (0xC0U) 1470 #define RTU_XRDC_MDA_W3_6_DFMT1_SA_SHIFT (6U) 1471 #define RTU_XRDC_MDA_W3_6_DFMT1_SA_WIDTH (2U) 1472 #define RTU_XRDC_MDA_W3_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_SA_MASK) 1473 1474 #define RTU_XRDC_MDA_W3_6_DFMT1_DIDB_MASK (0x100U) 1475 #define RTU_XRDC_MDA_W3_6_DFMT1_DIDB_SHIFT (8U) 1476 #define RTU_XRDC_MDA_W3_6_DFMT1_DIDB_WIDTH (1U) 1477 #define RTU_XRDC_MDA_W3_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_DIDB_MASK) 1478 1479 #define RTU_XRDC_MDA_W3_6_DFMT1_LPID_MASK (0xF000000U) 1480 #define RTU_XRDC_MDA_W3_6_DFMT1_LPID_SHIFT (24U) 1481 #define RTU_XRDC_MDA_W3_6_DFMT1_LPID_WIDTH (4U) 1482 #define RTU_XRDC_MDA_W3_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_LPID_MASK) 1483 1484 #define RTU_XRDC_MDA_W3_6_DFMT1_LPE_MASK (0x10000000U) 1485 #define RTU_XRDC_MDA_W3_6_DFMT1_LPE_SHIFT (28U) 1486 #define RTU_XRDC_MDA_W3_6_DFMT1_LPE_WIDTH (1U) 1487 #define RTU_XRDC_MDA_W3_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_LPE_MASK) 1488 1489 #define RTU_XRDC_MDA_W3_6_DFMT1_DFMT_MASK (0x20000000U) 1490 #define RTU_XRDC_MDA_W3_6_DFMT1_DFMT_SHIFT (29U) 1491 #define RTU_XRDC_MDA_W3_6_DFMT1_DFMT_WIDTH (1U) 1492 #define RTU_XRDC_MDA_W3_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_DFMT_MASK) 1493 1494 #define RTU_XRDC_MDA_W3_6_DFMT1_LK1_MASK (0x40000000U) 1495 #define RTU_XRDC_MDA_W3_6_DFMT1_LK1_SHIFT (30U) 1496 #define RTU_XRDC_MDA_W3_6_DFMT1_LK1_WIDTH (1U) 1497 #define RTU_XRDC_MDA_W3_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_LK1_MASK) 1498 1499 #define RTU_XRDC_MDA_W3_6_DFMT1_VLD_MASK (0x80000000U) 1500 #define RTU_XRDC_MDA_W3_6_DFMT1_VLD_SHIFT (31U) 1501 #define RTU_XRDC_MDA_W3_6_DFMT1_VLD_WIDTH (1U) 1502 #define RTU_XRDC_MDA_W3_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_6_DFMT1_VLD_MASK) 1503 /*! @} */ 1504 1505 /*! @name MDA_W4_6_DFMT1 - Master Domain Assignment */ 1506 /*! @{ */ 1507 1508 #define RTU_XRDC_MDA_W4_6_DFMT1_DID_MASK (0xFU) 1509 #define RTU_XRDC_MDA_W4_6_DFMT1_DID_SHIFT (0U) 1510 #define RTU_XRDC_MDA_W4_6_DFMT1_DID_WIDTH (4U) 1511 #define RTU_XRDC_MDA_W4_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_DID_MASK) 1512 1513 #define RTU_XRDC_MDA_W4_6_DFMT1_PA_MASK (0x30U) 1514 #define RTU_XRDC_MDA_W4_6_DFMT1_PA_SHIFT (4U) 1515 #define RTU_XRDC_MDA_W4_6_DFMT1_PA_WIDTH (2U) 1516 #define RTU_XRDC_MDA_W4_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_PA_MASK) 1517 1518 #define RTU_XRDC_MDA_W4_6_DFMT1_SA_MASK (0xC0U) 1519 #define RTU_XRDC_MDA_W4_6_DFMT1_SA_SHIFT (6U) 1520 #define RTU_XRDC_MDA_W4_6_DFMT1_SA_WIDTH (2U) 1521 #define RTU_XRDC_MDA_W4_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_SA_MASK) 1522 1523 #define RTU_XRDC_MDA_W4_6_DFMT1_DIDB_MASK (0x100U) 1524 #define RTU_XRDC_MDA_W4_6_DFMT1_DIDB_SHIFT (8U) 1525 #define RTU_XRDC_MDA_W4_6_DFMT1_DIDB_WIDTH (1U) 1526 #define RTU_XRDC_MDA_W4_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_DIDB_MASK) 1527 1528 #define RTU_XRDC_MDA_W4_6_DFMT1_LPID_MASK (0xF000000U) 1529 #define RTU_XRDC_MDA_W4_6_DFMT1_LPID_SHIFT (24U) 1530 #define RTU_XRDC_MDA_W4_6_DFMT1_LPID_WIDTH (4U) 1531 #define RTU_XRDC_MDA_W4_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_LPID_MASK) 1532 1533 #define RTU_XRDC_MDA_W4_6_DFMT1_LPE_MASK (0x10000000U) 1534 #define RTU_XRDC_MDA_W4_6_DFMT1_LPE_SHIFT (28U) 1535 #define RTU_XRDC_MDA_W4_6_DFMT1_LPE_WIDTH (1U) 1536 #define RTU_XRDC_MDA_W4_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_LPE_MASK) 1537 1538 #define RTU_XRDC_MDA_W4_6_DFMT1_DFMT_MASK (0x20000000U) 1539 #define RTU_XRDC_MDA_W4_6_DFMT1_DFMT_SHIFT (29U) 1540 #define RTU_XRDC_MDA_W4_6_DFMT1_DFMT_WIDTH (1U) 1541 #define RTU_XRDC_MDA_W4_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_DFMT_MASK) 1542 1543 #define RTU_XRDC_MDA_W4_6_DFMT1_LK1_MASK (0x40000000U) 1544 #define RTU_XRDC_MDA_W4_6_DFMT1_LK1_SHIFT (30U) 1545 #define RTU_XRDC_MDA_W4_6_DFMT1_LK1_WIDTH (1U) 1546 #define RTU_XRDC_MDA_W4_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_LK1_MASK) 1547 1548 #define RTU_XRDC_MDA_W4_6_DFMT1_VLD_MASK (0x80000000U) 1549 #define RTU_XRDC_MDA_W4_6_DFMT1_VLD_SHIFT (31U) 1550 #define RTU_XRDC_MDA_W4_6_DFMT1_VLD_WIDTH (1U) 1551 #define RTU_XRDC_MDA_W4_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_6_DFMT1_VLD_MASK) 1552 /*! @} */ 1553 1554 /*! @name MDA_W5_6_DFMT1 - Master Domain Assignment */ 1555 /*! @{ */ 1556 1557 #define RTU_XRDC_MDA_W5_6_DFMT1_DID_MASK (0xFU) 1558 #define RTU_XRDC_MDA_W5_6_DFMT1_DID_SHIFT (0U) 1559 #define RTU_XRDC_MDA_W5_6_DFMT1_DID_WIDTH (4U) 1560 #define RTU_XRDC_MDA_W5_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_DID_MASK) 1561 1562 #define RTU_XRDC_MDA_W5_6_DFMT1_PA_MASK (0x30U) 1563 #define RTU_XRDC_MDA_W5_6_DFMT1_PA_SHIFT (4U) 1564 #define RTU_XRDC_MDA_W5_6_DFMT1_PA_WIDTH (2U) 1565 #define RTU_XRDC_MDA_W5_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_PA_MASK) 1566 1567 #define RTU_XRDC_MDA_W5_6_DFMT1_SA_MASK (0xC0U) 1568 #define RTU_XRDC_MDA_W5_6_DFMT1_SA_SHIFT (6U) 1569 #define RTU_XRDC_MDA_W5_6_DFMT1_SA_WIDTH (2U) 1570 #define RTU_XRDC_MDA_W5_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_SA_MASK) 1571 1572 #define RTU_XRDC_MDA_W5_6_DFMT1_DIDB_MASK (0x100U) 1573 #define RTU_XRDC_MDA_W5_6_DFMT1_DIDB_SHIFT (8U) 1574 #define RTU_XRDC_MDA_W5_6_DFMT1_DIDB_WIDTH (1U) 1575 #define RTU_XRDC_MDA_W5_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_DIDB_MASK) 1576 1577 #define RTU_XRDC_MDA_W5_6_DFMT1_LPID_MASK (0xF000000U) 1578 #define RTU_XRDC_MDA_W5_6_DFMT1_LPID_SHIFT (24U) 1579 #define RTU_XRDC_MDA_W5_6_DFMT1_LPID_WIDTH (4U) 1580 #define RTU_XRDC_MDA_W5_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_LPID_MASK) 1581 1582 #define RTU_XRDC_MDA_W5_6_DFMT1_LPE_MASK (0x10000000U) 1583 #define RTU_XRDC_MDA_W5_6_DFMT1_LPE_SHIFT (28U) 1584 #define RTU_XRDC_MDA_W5_6_DFMT1_LPE_WIDTH (1U) 1585 #define RTU_XRDC_MDA_W5_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_LPE_MASK) 1586 1587 #define RTU_XRDC_MDA_W5_6_DFMT1_DFMT_MASK (0x20000000U) 1588 #define RTU_XRDC_MDA_W5_6_DFMT1_DFMT_SHIFT (29U) 1589 #define RTU_XRDC_MDA_W5_6_DFMT1_DFMT_WIDTH (1U) 1590 #define RTU_XRDC_MDA_W5_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_DFMT_MASK) 1591 1592 #define RTU_XRDC_MDA_W5_6_DFMT1_LK1_MASK (0x40000000U) 1593 #define RTU_XRDC_MDA_W5_6_DFMT1_LK1_SHIFT (30U) 1594 #define RTU_XRDC_MDA_W5_6_DFMT1_LK1_WIDTH (1U) 1595 #define RTU_XRDC_MDA_W5_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_LK1_MASK) 1596 1597 #define RTU_XRDC_MDA_W5_6_DFMT1_VLD_MASK (0x80000000U) 1598 #define RTU_XRDC_MDA_W5_6_DFMT1_VLD_SHIFT (31U) 1599 #define RTU_XRDC_MDA_W5_6_DFMT1_VLD_WIDTH (1U) 1600 #define RTU_XRDC_MDA_W5_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_6_DFMT1_VLD_MASK) 1601 /*! @} */ 1602 1603 /*! @name MDA_W6_6_DFMT1 - Master Domain Assignment */ 1604 /*! @{ */ 1605 1606 #define RTU_XRDC_MDA_W6_6_DFMT1_DID_MASK (0xFU) 1607 #define RTU_XRDC_MDA_W6_6_DFMT1_DID_SHIFT (0U) 1608 #define RTU_XRDC_MDA_W6_6_DFMT1_DID_WIDTH (4U) 1609 #define RTU_XRDC_MDA_W6_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_DID_MASK) 1610 1611 #define RTU_XRDC_MDA_W6_6_DFMT1_PA_MASK (0x30U) 1612 #define RTU_XRDC_MDA_W6_6_DFMT1_PA_SHIFT (4U) 1613 #define RTU_XRDC_MDA_W6_6_DFMT1_PA_WIDTH (2U) 1614 #define RTU_XRDC_MDA_W6_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_PA_MASK) 1615 1616 #define RTU_XRDC_MDA_W6_6_DFMT1_SA_MASK (0xC0U) 1617 #define RTU_XRDC_MDA_W6_6_DFMT1_SA_SHIFT (6U) 1618 #define RTU_XRDC_MDA_W6_6_DFMT1_SA_WIDTH (2U) 1619 #define RTU_XRDC_MDA_W6_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_SA_MASK) 1620 1621 #define RTU_XRDC_MDA_W6_6_DFMT1_DIDB_MASK (0x100U) 1622 #define RTU_XRDC_MDA_W6_6_DFMT1_DIDB_SHIFT (8U) 1623 #define RTU_XRDC_MDA_W6_6_DFMT1_DIDB_WIDTH (1U) 1624 #define RTU_XRDC_MDA_W6_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_DIDB_MASK) 1625 1626 #define RTU_XRDC_MDA_W6_6_DFMT1_LPID_MASK (0xF000000U) 1627 #define RTU_XRDC_MDA_W6_6_DFMT1_LPID_SHIFT (24U) 1628 #define RTU_XRDC_MDA_W6_6_DFMT1_LPID_WIDTH (4U) 1629 #define RTU_XRDC_MDA_W6_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_LPID_MASK) 1630 1631 #define RTU_XRDC_MDA_W6_6_DFMT1_LPE_MASK (0x10000000U) 1632 #define RTU_XRDC_MDA_W6_6_DFMT1_LPE_SHIFT (28U) 1633 #define RTU_XRDC_MDA_W6_6_DFMT1_LPE_WIDTH (1U) 1634 #define RTU_XRDC_MDA_W6_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_LPE_MASK) 1635 1636 #define RTU_XRDC_MDA_W6_6_DFMT1_DFMT_MASK (0x20000000U) 1637 #define RTU_XRDC_MDA_W6_6_DFMT1_DFMT_SHIFT (29U) 1638 #define RTU_XRDC_MDA_W6_6_DFMT1_DFMT_WIDTH (1U) 1639 #define RTU_XRDC_MDA_W6_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_DFMT_MASK) 1640 1641 #define RTU_XRDC_MDA_W6_6_DFMT1_LK1_MASK (0x40000000U) 1642 #define RTU_XRDC_MDA_W6_6_DFMT1_LK1_SHIFT (30U) 1643 #define RTU_XRDC_MDA_W6_6_DFMT1_LK1_WIDTH (1U) 1644 #define RTU_XRDC_MDA_W6_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_LK1_MASK) 1645 1646 #define RTU_XRDC_MDA_W6_6_DFMT1_VLD_MASK (0x80000000U) 1647 #define RTU_XRDC_MDA_W6_6_DFMT1_VLD_SHIFT (31U) 1648 #define RTU_XRDC_MDA_W6_6_DFMT1_VLD_WIDTH (1U) 1649 #define RTU_XRDC_MDA_W6_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_6_DFMT1_VLD_MASK) 1650 /*! @} */ 1651 1652 /*! @name MDA_W7_6_DFMT1 - Master Domain Assignment */ 1653 /*! @{ */ 1654 1655 #define RTU_XRDC_MDA_W7_6_DFMT1_DID_MASK (0xFU) 1656 #define RTU_XRDC_MDA_W7_6_DFMT1_DID_SHIFT (0U) 1657 #define RTU_XRDC_MDA_W7_6_DFMT1_DID_WIDTH (4U) 1658 #define RTU_XRDC_MDA_W7_6_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_DID_MASK) 1659 1660 #define RTU_XRDC_MDA_W7_6_DFMT1_PA_MASK (0x30U) 1661 #define RTU_XRDC_MDA_W7_6_DFMT1_PA_SHIFT (4U) 1662 #define RTU_XRDC_MDA_W7_6_DFMT1_PA_WIDTH (2U) 1663 #define RTU_XRDC_MDA_W7_6_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_PA_MASK) 1664 1665 #define RTU_XRDC_MDA_W7_6_DFMT1_SA_MASK (0xC0U) 1666 #define RTU_XRDC_MDA_W7_6_DFMT1_SA_SHIFT (6U) 1667 #define RTU_XRDC_MDA_W7_6_DFMT1_SA_WIDTH (2U) 1668 #define RTU_XRDC_MDA_W7_6_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_SA_MASK) 1669 1670 #define RTU_XRDC_MDA_W7_6_DFMT1_DIDB_MASK (0x100U) 1671 #define RTU_XRDC_MDA_W7_6_DFMT1_DIDB_SHIFT (8U) 1672 #define RTU_XRDC_MDA_W7_6_DFMT1_DIDB_WIDTH (1U) 1673 #define RTU_XRDC_MDA_W7_6_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_DIDB_MASK) 1674 1675 #define RTU_XRDC_MDA_W7_6_DFMT1_LPID_MASK (0xF000000U) 1676 #define RTU_XRDC_MDA_W7_6_DFMT1_LPID_SHIFT (24U) 1677 #define RTU_XRDC_MDA_W7_6_DFMT1_LPID_WIDTH (4U) 1678 #define RTU_XRDC_MDA_W7_6_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_LPID_MASK) 1679 1680 #define RTU_XRDC_MDA_W7_6_DFMT1_LPE_MASK (0x10000000U) 1681 #define RTU_XRDC_MDA_W7_6_DFMT1_LPE_SHIFT (28U) 1682 #define RTU_XRDC_MDA_W7_6_DFMT1_LPE_WIDTH (1U) 1683 #define RTU_XRDC_MDA_W7_6_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_LPE_MASK) 1684 1685 #define RTU_XRDC_MDA_W7_6_DFMT1_DFMT_MASK (0x20000000U) 1686 #define RTU_XRDC_MDA_W7_6_DFMT1_DFMT_SHIFT (29U) 1687 #define RTU_XRDC_MDA_W7_6_DFMT1_DFMT_WIDTH (1U) 1688 #define RTU_XRDC_MDA_W7_6_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_DFMT_MASK) 1689 1690 #define RTU_XRDC_MDA_W7_6_DFMT1_LK1_MASK (0x40000000U) 1691 #define RTU_XRDC_MDA_W7_6_DFMT1_LK1_SHIFT (30U) 1692 #define RTU_XRDC_MDA_W7_6_DFMT1_LK1_WIDTH (1U) 1693 #define RTU_XRDC_MDA_W7_6_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_LK1_MASK) 1694 1695 #define RTU_XRDC_MDA_W7_6_DFMT1_VLD_MASK (0x80000000U) 1696 #define RTU_XRDC_MDA_W7_6_DFMT1_VLD_SHIFT (31U) 1697 #define RTU_XRDC_MDA_W7_6_DFMT1_VLD_WIDTH (1U) 1698 #define RTU_XRDC_MDA_W7_6_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_6_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_6_DFMT1_VLD_MASK) 1699 /*! @} */ 1700 1701 /*! @name MDA_W0_7_DFMT1 - Master Domain Assignment */ 1702 /*! @{ */ 1703 1704 #define RTU_XRDC_MDA_W0_7_DFMT1_DID_MASK (0xFU) 1705 #define RTU_XRDC_MDA_W0_7_DFMT1_DID_SHIFT (0U) 1706 #define RTU_XRDC_MDA_W0_7_DFMT1_DID_WIDTH (4U) 1707 #define RTU_XRDC_MDA_W0_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_DID_MASK) 1708 1709 #define RTU_XRDC_MDA_W0_7_DFMT1_PA_MASK (0x30U) 1710 #define RTU_XRDC_MDA_W0_7_DFMT1_PA_SHIFT (4U) 1711 #define RTU_XRDC_MDA_W0_7_DFMT1_PA_WIDTH (2U) 1712 #define RTU_XRDC_MDA_W0_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_PA_MASK) 1713 1714 #define RTU_XRDC_MDA_W0_7_DFMT1_SA_MASK (0xC0U) 1715 #define RTU_XRDC_MDA_W0_7_DFMT1_SA_SHIFT (6U) 1716 #define RTU_XRDC_MDA_W0_7_DFMT1_SA_WIDTH (2U) 1717 #define RTU_XRDC_MDA_W0_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_SA_MASK) 1718 1719 #define RTU_XRDC_MDA_W0_7_DFMT1_DIDB_MASK (0x100U) 1720 #define RTU_XRDC_MDA_W0_7_DFMT1_DIDB_SHIFT (8U) 1721 #define RTU_XRDC_MDA_W0_7_DFMT1_DIDB_WIDTH (1U) 1722 #define RTU_XRDC_MDA_W0_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_DIDB_MASK) 1723 1724 #define RTU_XRDC_MDA_W0_7_DFMT1_LPID_MASK (0xF000000U) 1725 #define RTU_XRDC_MDA_W0_7_DFMT1_LPID_SHIFT (24U) 1726 #define RTU_XRDC_MDA_W0_7_DFMT1_LPID_WIDTH (4U) 1727 #define RTU_XRDC_MDA_W0_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_LPID_MASK) 1728 1729 #define RTU_XRDC_MDA_W0_7_DFMT1_LPE_MASK (0x10000000U) 1730 #define RTU_XRDC_MDA_W0_7_DFMT1_LPE_SHIFT (28U) 1731 #define RTU_XRDC_MDA_W0_7_DFMT1_LPE_WIDTH (1U) 1732 #define RTU_XRDC_MDA_W0_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_LPE_MASK) 1733 1734 #define RTU_XRDC_MDA_W0_7_DFMT1_DFMT_MASK (0x20000000U) 1735 #define RTU_XRDC_MDA_W0_7_DFMT1_DFMT_SHIFT (29U) 1736 #define RTU_XRDC_MDA_W0_7_DFMT1_DFMT_WIDTH (1U) 1737 #define RTU_XRDC_MDA_W0_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_DFMT_MASK) 1738 1739 #define RTU_XRDC_MDA_W0_7_DFMT1_LK1_MASK (0x40000000U) 1740 #define RTU_XRDC_MDA_W0_7_DFMT1_LK1_SHIFT (30U) 1741 #define RTU_XRDC_MDA_W0_7_DFMT1_LK1_WIDTH (1U) 1742 #define RTU_XRDC_MDA_W0_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_LK1_MASK) 1743 1744 #define RTU_XRDC_MDA_W0_7_DFMT1_VLD_MASK (0x80000000U) 1745 #define RTU_XRDC_MDA_W0_7_DFMT1_VLD_SHIFT (31U) 1746 #define RTU_XRDC_MDA_W0_7_DFMT1_VLD_WIDTH (1U) 1747 #define RTU_XRDC_MDA_W0_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_7_DFMT1_VLD_MASK) 1748 /*! @} */ 1749 1750 /*! @name MDA_W1_7_DFMT1 - Master Domain Assignment */ 1751 /*! @{ */ 1752 1753 #define RTU_XRDC_MDA_W1_7_DFMT1_DID_MASK (0xFU) 1754 #define RTU_XRDC_MDA_W1_7_DFMT1_DID_SHIFT (0U) 1755 #define RTU_XRDC_MDA_W1_7_DFMT1_DID_WIDTH (4U) 1756 #define RTU_XRDC_MDA_W1_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_DID_MASK) 1757 1758 #define RTU_XRDC_MDA_W1_7_DFMT1_PA_MASK (0x30U) 1759 #define RTU_XRDC_MDA_W1_7_DFMT1_PA_SHIFT (4U) 1760 #define RTU_XRDC_MDA_W1_7_DFMT1_PA_WIDTH (2U) 1761 #define RTU_XRDC_MDA_W1_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_PA_MASK) 1762 1763 #define RTU_XRDC_MDA_W1_7_DFMT1_SA_MASK (0xC0U) 1764 #define RTU_XRDC_MDA_W1_7_DFMT1_SA_SHIFT (6U) 1765 #define RTU_XRDC_MDA_W1_7_DFMT1_SA_WIDTH (2U) 1766 #define RTU_XRDC_MDA_W1_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_SA_MASK) 1767 1768 #define RTU_XRDC_MDA_W1_7_DFMT1_DIDB_MASK (0x100U) 1769 #define RTU_XRDC_MDA_W1_7_DFMT1_DIDB_SHIFT (8U) 1770 #define RTU_XRDC_MDA_W1_7_DFMT1_DIDB_WIDTH (1U) 1771 #define RTU_XRDC_MDA_W1_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_DIDB_MASK) 1772 1773 #define RTU_XRDC_MDA_W1_7_DFMT1_LPID_MASK (0xF000000U) 1774 #define RTU_XRDC_MDA_W1_7_DFMT1_LPID_SHIFT (24U) 1775 #define RTU_XRDC_MDA_W1_7_DFMT1_LPID_WIDTH (4U) 1776 #define RTU_XRDC_MDA_W1_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_LPID_MASK) 1777 1778 #define RTU_XRDC_MDA_W1_7_DFMT1_LPE_MASK (0x10000000U) 1779 #define RTU_XRDC_MDA_W1_7_DFMT1_LPE_SHIFT (28U) 1780 #define RTU_XRDC_MDA_W1_7_DFMT1_LPE_WIDTH (1U) 1781 #define RTU_XRDC_MDA_W1_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_LPE_MASK) 1782 1783 #define RTU_XRDC_MDA_W1_7_DFMT1_DFMT_MASK (0x20000000U) 1784 #define RTU_XRDC_MDA_W1_7_DFMT1_DFMT_SHIFT (29U) 1785 #define RTU_XRDC_MDA_W1_7_DFMT1_DFMT_WIDTH (1U) 1786 #define RTU_XRDC_MDA_W1_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_DFMT_MASK) 1787 1788 #define RTU_XRDC_MDA_W1_7_DFMT1_LK1_MASK (0x40000000U) 1789 #define RTU_XRDC_MDA_W1_7_DFMT1_LK1_SHIFT (30U) 1790 #define RTU_XRDC_MDA_W1_7_DFMT1_LK1_WIDTH (1U) 1791 #define RTU_XRDC_MDA_W1_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_LK1_MASK) 1792 1793 #define RTU_XRDC_MDA_W1_7_DFMT1_VLD_MASK (0x80000000U) 1794 #define RTU_XRDC_MDA_W1_7_DFMT1_VLD_SHIFT (31U) 1795 #define RTU_XRDC_MDA_W1_7_DFMT1_VLD_WIDTH (1U) 1796 #define RTU_XRDC_MDA_W1_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_7_DFMT1_VLD_MASK) 1797 /*! @} */ 1798 1799 /*! @name MDA_W2_7_DFMT1 - Master Domain Assignment */ 1800 /*! @{ */ 1801 1802 #define RTU_XRDC_MDA_W2_7_DFMT1_DID_MASK (0xFU) 1803 #define RTU_XRDC_MDA_W2_7_DFMT1_DID_SHIFT (0U) 1804 #define RTU_XRDC_MDA_W2_7_DFMT1_DID_WIDTH (4U) 1805 #define RTU_XRDC_MDA_W2_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_DID_MASK) 1806 1807 #define RTU_XRDC_MDA_W2_7_DFMT1_PA_MASK (0x30U) 1808 #define RTU_XRDC_MDA_W2_7_DFMT1_PA_SHIFT (4U) 1809 #define RTU_XRDC_MDA_W2_7_DFMT1_PA_WIDTH (2U) 1810 #define RTU_XRDC_MDA_W2_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_PA_MASK) 1811 1812 #define RTU_XRDC_MDA_W2_7_DFMT1_SA_MASK (0xC0U) 1813 #define RTU_XRDC_MDA_W2_7_DFMT1_SA_SHIFT (6U) 1814 #define RTU_XRDC_MDA_W2_7_DFMT1_SA_WIDTH (2U) 1815 #define RTU_XRDC_MDA_W2_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_SA_MASK) 1816 1817 #define RTU_XRDC_MDA_W2_7_DFMT1_DIDB_MASK (0x100U) 1818 #define RTU_XRDC_MDA_W2_7_DFMT1_DIDB_SHIFT (8U) 1819 #define RTU_XRDC_MDA_W2_7_DFMT1_DIDB_WIDTH (1U) 1820 #define RTU_XRDC_MDA_W2_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_DIDB_MASK) 1821 1822 #define RTU_XRDC_MDA_W2_7_DFMT1_LPID_MASK (0xF000000U) 1823 #define RTU_XRDC_MDA_W2_7_DFMT1_LPID_SHIFT (24U) 1824 #define RTU_XRDC_MDA_W2_7_DFMT1_LPID_WIDTH (4U) 1825 #define RTU_XRDC_MDA_W2_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_LPID_MASK) 1826 1827 #define RTU_XRDC_MDA_W2_7_DFMT1_LPE_MASK (0x10000000U) 1828 #define RTU_XRDC_MDA_W2_7_DFMT1_LPE_SHIFT (28U) 1829 #define RTU_XRDC_MDA_W2_7_DFMT1_LPE_WIDTH (1U) 1830 #define RTU_XRDC_MDA_W2_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_LPE_MASK) 1831 1832 #define RTU_XRDC_MDA_W2_7_DFMT1_DFMT_MASK (0x20000000U) 1833 #define RTU_XRDC_MDA_W2_7_DFMT1_DFMT_SHIFT (29U) 1834 #define RTU_XRDC_MDA_W2_7_DFMT1_DFMT_WIDTH (1U) 1835 #define RTU_XRDC_MDA_W2_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_DFMT_MASK) 1836 1837 #define RTU_XRDC_MDA_W2_7_DFMT1_LK1_MASK (0x40000000U) 1838 #define RTU_XRDC_MDA_W2_7_DFMT1_LK1_SHIFT (30U) 1839 #define RTU_XRDC_MDA_W2_7_DFMT1_LK1_WIDTH (1U) 1840 #define RTU_XRDC_MDA_W2_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_LK1_MASK) 1841 1842 #define RTU_XRDC_MDA_W2_7_DFMT1_VLD_MASK (0x80000000U) 1843 #define RTU_XRDC_MDA_W2_7_DFMT1_VLD_SHIFT (31U) 1844 #define RTU_XRDC_MDA_W2_7_DFMT1_VLD_WIDTH (1U) 1845 #define RTU_XRDC_MDA_W2_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_7_DFMT1_VLD_MASK) 1846 /*! @} */ 1847 1848 /*! @name MDA_W3_7_DFMT1 - Master Domain Assignment */ 1849 /*! @{ */ 1850 1851 #define RTU_XRDC_MDA_W3_7_DFMT1_DID_MASK (0xFU) 1852 #define RTU_XRDC_MDA_W3_7_DFMT1_DID_SHIFT (0U) 1853 #define RTU_XRDC_MDA_W3_7_DFMT1_DID_WIDTH (4U) 1854 #define RTU_XRDC_MDA_W3_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_DID_MASK) 1855 1856 #define RTU_XRDC_MDA_W3_7_DFMT1_PA_MASK (0x30U) 1857 #define RTU_XRDC_MDA_W3_7_DFMT1_PA_SHIFT (4U) 1858 #define RTU_XRDC_MDA_W3_7_DFMT1_PA_WIDTH (2U) 1859 #define RTU_XRDC_MDA_W3_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_PA_MASK) 1860 1861 #define RTU_XRDC_MDA_W3_7_DFMT1_SA_MASK (0xC0U) 1862 #define RTU_XRDC_MDA_W3_7_DFMT1_SA_SHIFT (6U) 1863 #define RTU_XRDC_MDA_W3_7_DFMT1_SA_WIDTH (2U) 1864 #define RTU_XRDC_MDA_W3_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_SA_MASK) 1865 1866 #define RTU_XRDC_MDA_W3_7_DFMT1_DIDB_MASK (0x100U) 1867 #define RTU_XRDC_MDA_W3_7_DFMT1_DIDB_SHIFT (8U) 1868 #define RTU_XRDC_MDA_W3_7_DFMT1_DIDB_WIDTH (1U) 1869 #define RTU_XRDC_MDA_W3_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_DIDB_MASK) 1870 1871 #define RTU_XRDC_MDA_W3_7_DFMT1_LPID_MASK (0xF000000U) 1872 #define RTU_XRDC_MDA_W3_7_DFMT1_LPID_SHIFT (24U) 1873 #define RTU_XRDC_MDA_W3_7_DFMT1_LPID_WIDTH (4U) 1874 #define RTU_XRDC_MDA_W3_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_LPID_MASK) 1875 1876 #define RTU_XRDC_MDA_W3_7_DFMT1_LPE_MASK (0x10000000U) 1877 #define RTU_XRDC_MDA_W3_7_DFMT1_LPE_SHIFT (28U) 1878 #define RTU_XRDC_MDA_W3_7_DFMT1_LPE_WIDTH (1U) 1879 #define RTU_XRDC_MDA_W3_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_LPE_MASK) 1880 1881 #define RTU_XRDC_MDA_W3_7_DFMT1_DFMT_MASK (0x20000000U) 1882 #define RTU_XRDC_MDA_W3_7_DFMT1_DFMT_SHIFT (29U) 1883 #define RTU_XRDC_MDA_W3_7_DFMT1_DFMT_WIDTH (1U) 1884 #define RTU_XRDC_MDA_W3_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_DFMT_MASK) 1885 1886 #define RTU_XRDC_MDA_W3_7_DFMT1_LK1_MASK (0x40000000U) 1887 #define RTU_XRDC_MDA_W3_7_DFMT1_LK1_SHIFT (30U) 1888 #define RTU_XRDC_MDA_W3_7_DFMT1_LK1_WIDTH (1U) 1889 #define RTU_XRDC_MDA_W3_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_LK1_MASK) 1890 1891 #define RTU_XRDC_MDA_W3_7_DFMT1_VLD_MASK (0x80000000U) 1892 #define RTU_XRDC_MDA_W3_7_DFMT1_VLD_SHIFT (31U) 1893 #define RTU_XRDC_MDA_W3_7_DFMT1_VLD_WIDTH (1U) 1894 #define RTU_XRDC_MDA_W3_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_7_DFMT1_VLD_MASK) 1895 /*! @} */ 1896 1897 /*! @name MDA_W4_7_DFMT1 - Master Domain Assignment */ 1898 /*! @{ */ 1899 1900 #define RTU_XRDC_MDA_W4_7_DFMT1_DID_MASK (0xFU) 1901 #define RTU_XRDC_MDA_W4_7_DFMT1_DID_SHIFT (0U) 1902 #define RTU_XRDC_MDA_W4_7_DFMT1_DID_WIDTH (4U) 1903 #define RTU_XRDC_MDA_W4_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_DID_MASK) 1904 1905 #define RTU_XRDC_MDA_W4_7_DFMT1_PA_MASK (0x30U) 1906 #define RTU_XRDC_MDA_W4_7_DFMT1_PA_SHIFT (4U) 1907 #define RTU_XRDC_MDA_W4_7_DFMT1_PA_WIDTH (2U) 1908 #define RTU_XRDC_MDA_W4_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_PA_MASK) 1909 1910 #define RTU_XRDC_MDA_W4_7_DFMT1_SA_MASK (0xC0U) 1911 #define RTU_XRDC_MDA_W4_7_DFMT1_SA_SHIFT (6U) 1912 #define RTU_XRDC_MDA_W4_7_DFMT1_SA_WIDTH (2U) 1913 #define RTU_XRDC_MDA_W4_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_SA_MASK) 1914 1915 #define RTU_XRDC_MDA_W4_7_DFMT1_DIDB_MASK (0x100U) 1916 #define RTU_XRDC_MDA_W4_7_DFMT1_DIDB_SHIFT (8U) 1917 #define RTU_XRDC_MDA_W4_7_DFMT1_DIDB_WIDTH (1U) 1918 #define RTU_XRDC_MDA_W4_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_DIDB_MASK) 1919 1920 #define RTU_XRDC_MDA_W4_7_DFMT1_LPID_MASK (0xF000000U) 1921 #define RTU_XRDC_MDA_W4_7_DFMT1_LPID_SHIFT (24U) 1922 #define RTU_XRDC_MDA_W4_7_DFMT1_LPID_WIDTH (4U) 1923 #define RTU_XRDC_MDA_W4_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_LPID_MASK) 1924 1925 #define RTU_XRDC_MDA_W4_7_DFMT1_LPE_MASK (0x10000000U) 1926 #define RTU_XRDC_MDA_W4_7_DFMT1_LPE_SHIFT (28U) 1927 #define RTU_XRDC_MDA_W4_7_DFMT1_LPE_WIDTH (1U) 1928 #define RTU_XRDC_MDA_W4_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_LPE_MASK) 1929 1930 #define RTU_XRDC_MDA_W4_7_DFMT1_DFMT_MASK (0x20000000U) 1931 #define RTU_XRDC_MDA_W4_7_DFMT1_DFMT_SHIFT (29U) 1932 #define RTU_XRDC_MDA_W4_7_DFMT1_DFMT_WIDTH (1U) 1933 #define RTU_XRDC_MDA_W4_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_DFMT_MASK) 1934 1935 #define RTU_XRDC_MDA_W4_7_DFMT1_LK1_MASK (0x40000000U) 1936 #define RTU_XRDC_MDA_W4_7_DFMT1_LK1_SHIFT (30U) 1937 #define RTU_XRDC_MDA_W4_7_DFMT1_LK1_WIDTH (1U) 1938 #define RTU_XRDC_MDA_W4_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_LK1_MASK) 1939 1940 #define RTU_XRDC_MDA_W4_7_DFMT1_VLD_MASK (0x80000000U) 1941 #define RTU_XRDC_MDA_W4_7_DFMT1_VLD_SHIFT (31U) 1942 #define RTU_XRDC_MDA_W4_7_DFMT1_VLD_WIDTH (1U) 1943 #define RTU_XRDC_MDA_W4_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_7_DFMT1_VLD_MASK) 1944 /*! @} */ 1945 1946 /*! @name MDA_W5_7_DFMT1 - Master Domain Assignment */ 1947 /*! @{ */ 1948 1949 #define RTU_XRDC_MDA_W5_7_DFMT1_DID_MASK (0xFU) 1950 #define RTU_XRDC_MDA_W5_7_DFMT1_DID_SHIFT (0U) 1951 #define RTU_XRDC_MDA_W5_7_DFMT1_DID_WIDTH (4U) 1952 #define RTU_XRDC_MDA_W5_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_DID_MASK) 1953 1954 #define RTU_XRDC_MDA_W5_7_DFMT1_PA_MASK (0x30U) 1955 #define RTU_XRDC_MDA_W5_7_DFMT1_PA_SHIFT (4U) 1956 #define RTU_XRDC_MDA_W5_7_DFMT1_PA_WIDTH (2U) 1957 #define RTU_XRDC_MDA_W5_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_PA_MASK) 1958 1959 #define RTU_XRDC_MDA_W5_7_DFMT1_SA_MASK (0xC0U) 1960 #define RTU_XRDC_MDA_W5_7_DFMT1_SA_SHIFT (6U) 1961 #define RTU_XRDC_MDA_W5_7_DFMT1_SA_WIDTH (2U) 1962 #define RTU_XRDC_MDA_W5_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_SA_MASK) 1963 1964 #define RTU_XRDC_MDA_W5_7_DFMT1_DIDB_MASK (0x100U) 1965 #define RTU_XRDC_MDA_W5_7_DFMT1_DIDB_SHIFT (8U) 1966 #define RTU_XRDC_MDA_W5_7_DFMT1_DIDB_WIDTH (1U) 1967 #define RTU_XRDC_MDA_W5_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_DIDB_MASK) 1968 1969 #define RTU_XRDC_MDA_W5_7_DFMT1_LPID_MASK (0xF000000U) 1970 #define RTU_XRDC_MDA_W5_7_DFMT1_LPID_SHIFT (24U) 1971 #define RTU_XRDC_MDA_W5_7_DFMT1_LPID_WIDTH (4U) 1972 #define RTU_XRDC_MDA_W5_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_LPID_MASK) 1973 1974 #define RTU_XRDC_MDA_W5_7_DFMT1_LPE_MASK (0x10000000U) 1975 #define RTU_XRDC_MDA_W5_7_DFMT1_LPE_SHIFT (28U) 1976 #define RTU_XRDC_MDA_W5_7_DFMT1_LPE_WIDTH (1U) 1977 #define RTU_XRDC_MDA_W5_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_LPE_MASK) 1978 1979 #define RTU_XRDC_MDA_W5_7_DFMT1_DFMT_MASK (0x20000000U) 1980 #define RTU_XRDC_MDA_W5_7_DFMT1_DFMT_SHIFT (29U) 1981 #define RTU_XRDC_MDA_W5_7_DFMT1_DFMT_WIDTH (1U) 1982 #define RTU_XRDC_MDA_W5_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_DFMT_MASK) 1983 1984 #define RTU_XRDC_MDA_W5_7_DFMT1_LK1_MASK (0x40000000U) 1985 #define RTU_XRDC_MDA_W5_7_DFMT1_LK1_SHIFT (30U) 1986 #define RTU_XRDC_MDA_W5_7_DFMT1_LK1_WIDTH (1U) 1987 #define RTU_XRDC_MDA_W5_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_LK1_MASK) 1988 1989 #define RTU_XRDC_MDA_W5_7_DFMT1_VLD_MASK (0x80000000U) 1990 #define RTU_XRDC_MDA_W5_7_DFMT1_VLD_SHIFT (31U) 1991 #define RTU_XRDC_MDA_W5_7_DFMT1_VLD_WIDTH (1U) 1992 #define RTU_XRDC_MDA_W5_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_7_DFMT1_VLD_MASK) 1993 /*! @} */ 1994 1995 /*! @name MDA_W6_7_DFMT1 - Master Domain Assignment */ 1996 /*! @{ */ 1997 1998 #define RTU_XRDC_MDA_W6_7_DFMT1_DID_MASK (0xFU) 1999 #define RTU_XRDC_MDA_W6_7_DFMT1_DID_SHIFT (0U) 2000 #define RTU_XRDC_MDA_W6_7_DFMT1_DID_WIDTH (4U) 2001 #define RTU_XRDC_MDA_W6_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_DID_MASK) 2002 2003 #define RTU_XRDC_MDA_W6_7_DFMT1_PA_MASK (0x30U) 2004 #define RTU_XRDC_MDA_W6_7_DFMT1_PA_SHIFT (4U) 2005 #define RTU_XRDC_MDA_W6_7_DFMT1_PA_WIDTH (2U) 2006 #define RTU_XRDC_MDA_W6_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_PA_MASK) 2007 2008 #define RTU_XRDC_MDA_W6_7_DFMT1_SA_MASK (0xC0U) 2009 #define RTU_XRDC_MDA_W6_7_DFMT1_SA_SHIFT (6U) 2010 #define RTU_XRDC_MDA_W6_7_DFMT1_SA_WIDTH (2U) 2011 #define RTU_XRDC_MDA_W6_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_SA_MASK) 2012 2013 #define RTU_XRDC_MDA_W6_7_DFMT1_DIDB_MASK (0x100U) 2014 #define RTU_XRDC_MDA_W6_7_DFMT1_DIDB_SHIFT (8U) 2015 #define RTU_XRDC_MDA_W6_7_DFMT1_DIDB_WIDTH (1U) 2016 #define RTU_XRDC_MDA_W6_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_DIDB_MASK) 2017 2018 #define RTU_XRDC_MDA_W6_7_DFMT1_LPID_MASK (0xF000000U) 2019 #define RTU_XRDC_MDA_W6_7_DFMT1_LPID_SHIFT (24U) 2020 #define RTU_XRDC_MDA_W6_7_DFMT1_LPID_WIDTH (4U) 2021 #define RTU_XRDC_MDA_W6_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_LPID_MASK) 2022 2023 #define RTU_XRDC_MDA_W6_7_DFMT1_LPE_MASK (0x10000000U) 2024 #define RTU_XRDC_MDA_W6_7_DFMT1_LPE_SHIFT (28U) 2025 #define RTU_XRDC_MDA_W6_7_DFMT1_LPE_WIDTH (1U) 2026 #define RTU_XRDC_MDA_W6_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_LPE_MASK) 2027 2028 #define RTU_XRDC_MDA_W6_7_DFMT1_DFMT_MASK (0x20000000U) 2029 #define RTU_XRDC_MDA_W6_7_DFMT1_DFMT_SHIFT (29U) 2030 #define RTU_XRDC_MDA_W6_7_DFMT1_DFMT_WIDTH (1U) 2031 #define RTU_XRDC_MDA_W6_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_DFMT_MASK) 2032 2033 #define RTU_XRDC_MDA_W6_7_DFMT1_LK1_MASK (0x40000000U) 2034 #define RTU_XRDC_MDA_W6_7_DFMT1_LK1_SHIFT (30U) 2035 #define RTU_XRDC_MDA_W6_7_DFMT1_LK1_WIDTH (1U) 2036 #define RTU_XRDC_MDA_W6_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_LK1_MASK) 2037 2038 #define RTU_XRDC_MDA_W6_7_DFMT1_VLD_MASK (0x80000000U) 2039 #define RTU_XRDC_MDA_W6_7_DFMT1_VLD_SHIFT (31U) 2040 #define RTU_XRDC_MDA_W6_7_DFMT1_VLD_WIDTH (1U) 2041 #define RTU_XRDC_MDA_W6_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_7_DFMT1_VLD_MASK) 2042 /*! @} */ 2043 2044 /*! @name MDA_W7_7_DFMT1 - Master Domain Assignment */ 2045 /*! @{ */ 2046 2047 #define RTU_XRDC_MDA_W7_7_DFMT1_DID_MASK (0xFU) 2048 #define RTU_XRDC_MDA_W7_7_DFMT1_DID_SHIFT (0U) 2049 #define RTU_XRDC_MDA_W7_7_DFMT1_DID_WIDTH (4U) 2050 #define RTU_XRDC_MDA_W7_7_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_DID_MASK) 2051 2052 #define RTU_XRDC_MDA_W7_7_DFMT1_PA_MASK (0x30U) 2053 #define RTU_XRDC_MDA_W7_7_DFMT1_PA_SHIFT (4U) 2054 #define RTU_XRDC_MDA_W7_7_DFMT1_PA_WIDTH (2U) 2055 #define RTU_XRDC_MDA_W7_7_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_PA_MASK) 2056 2057 #define RTU_XRDC_MDA_W7_7_DFMT1_SA_MASK (0xC0U) 2058 #define RTU_XRDC_MDA_W7_7_DFMT1_SA_SHIFT (6U) 2059 #define RTU_XRDC_MDA_W7_7_DFMT1_SA_WIDTH (2U) 2060 #define RTU_XRDC_MDA_W7_7_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_SA_MASK) 2061 2062 #define RTU_XRDC_MDA_W7_7_DFMT1_DIDB_MASK (0x100U) 2063 #define RTU_XRDC_MDA_W7_7_DFMT1_DIDB_SHIFT (8U) 2064 #define RTU_XRDC_MDA_W7_7_DFMT1_DIDB_WIDTH (1U) 2065 #define RTU_XRDC_MDA_W7_7_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_DIDB_MASK) 2066 2067 #define RTU_XRDC_MDA_W7_7_DFMT1_LPID_MASK (0xF000000U) 2068 #define RTU_XRDC_MDA_W7_7_DFMT1_LPID_SHIFT (24U) 2069 #define RTU_XRDC_MDA_W7_7_DFMT1_LPID_WIDTH (4U) 2070 #define RTU_XRDC_MDA_W7_7_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_LPID_MASK) 2071 2072 #define RTU_XRDC_MDA_W7_7_DFMT1_LPE_MASK (0x10000000U) 2073 #define RTU_XRDC_MDA_W7_7_DFMT1_LPE_SHIFT (28U) 2074 #define RTU_XRDC_MDA_W7_7_DFMT1_LPE_WIDTH (1U) 2075 #define RTU_XRDC_MDA_W7_7_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_LPE_MASK) 2076 2077 #define RTU_XRDC_MDA_W7_7_DFMT1_DFMT_MASK (0x20000000U) 2078 #define RTU_XRDC_MDA_W7_7_DFMT1_DFMT_SHIFT (29U) 2079 #define RTU_XRDC_MDA_W7_7_DFMT1_DFMT_WIDTH (1U) 2080 #define RTU_XRDC_MDA_W7_7_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_DFMT_MASK) 2081 2082 #define RTU_XRDC_MDA_W7_7_DFMT1_LK1_MASK (0x40000000U) 2083 #define RTU_XRDC_MDA_W7_7_DFMT1_LK1_SHIFT (30U) 2084 #define RTU_XRDC_MDA_W7_7_DFMT1_LK1_WIDTH (1U) 2085 #define RTU_XRDC_MDA_W7_7_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_LK1_MASK) 2086 2087 #define RTU_XRDC_MDA_W7_7_DFMT1_VLD_MASK (0x80000000U) 2088 #define RTU_XRDC_MDA_W7_7_DFMT1_VLD_SHIFT (31U) 2089 #define RTU_XRDC_MDA_W7_7_DFMT1_VLD_WIDTH (1U) 2090 #define RTU_XRDC_MDA_W7_7_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_7_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_7_DFMT1_VLD_MASK) 2091 /*! @} */ 2092 2093 /*! @name MDA_W0_8_DFMT1 - Master Domain Assignment */ 2094 /*! @{ */ 2095 2096 #define RTU_XRDC_MDA_W0_8_DFMT1_DID_MASK (0xFU) 2097 #define RTU_XRDC_MDA_W0_8_DFMT1_DID_SHIFT (0U) 2098 #define RTU_XRDC_MDA_W0_8_DFMT1_DID_WIDTH (4U) 2099 #define RTU_XRDC_MDA_W0_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_DID_MASK) 2100 2101 #define RTU_XRDC_MDA_W0_8_DFMT1_PA_MASK (0x30U) 2102 #define RTU_XRDC_MDA_W0_8_DFMT1_PA_SHIFT (4U) 2103 #define RTU_XRDC_MDA_W0_8_DFMT1_PA_WIDTH (2U) 2104 #define RTU_XRDC_MDA_W0_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_PA_MASK) 2105 2106 #define RTU_XRDC_MDA_W0_8_DFMT1_SA_MASK (0xC0U) 2107 #define RTU_XRDC_MDA_W0_8_DFMT1_SA_SHIFT (6U) 2108 #define RTU_XRDC_MDA_W0_8_DFMT1_SA_WIDTH (2U) 2109 #define RTU_XRDC_MDA_W0_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_SA_MASK) 2110 2111 #define RTU_XRDC_MDA_W0_8_DFMT1_DIDB_MASK (0x100U) 2112 #define RTU_XRDC_MDA_W0_8_DFMT1_DIDB_SHIFT (8U) 2113 #define RTU_XRDC_MDA_W0_8_DFMT1_DIDB_WIDTH (1U) 2114 #define RTU_XRDC_MDA_W0_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_DIDB_MASK) 2115 2116 #define RTU_XRDC_MDA_W0_8_DFMT1_LPID_MASK (0xF000000U) 2117 #define RTU_XRDC_MDA_W0_8_DFMT1_LPID_SHIFT (24U) 2118 #define RTU_XRDC_MDA_W0_8_DFMT1_LPID_WIDTH (4U) 2119 #define RTU_XRDC_MDA_W0_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_LPID_MASK) 2120 2121 #define RTU_XRDC_MDA_W0_8_DFMT1_LPE_MASK (0x10000000U) 2122 #define RTU_XRDC_MDA_W0_8_DFMT1_LPE_SHIFT (28U) 2123 #define RTU_XRDC_MDA_W0_8_DFMT1_LPE_WIDTH (1U) 2124 #define RTU_XRDC_MDA_W0_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_LPE_MASK) 2125 2126 #define RTU_XRDC_MDA_W0_8_DFMT1_DFMT_MASK (0x20000000U) 2127 #define RTU_XRDC_MDA_W0_8_DFMT1_DFMT_SHIFT (29U) 2128 #define RTU_XRDC_MDA_W0_8_DFMT1_DFMT_WIDTH (1U) 2129 #define RTU_XRDC_MDA_W0_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_DFMT_MASK) 2130 2131 #define RTU_XRDC_MDA_W0_8_DFMT1_LK1_MASK (0x40000000U) 2132 #define RTU_XRDC_MDA_W0_8_DFMT1_LK1_SHIFT (30U) 2133 #define RTU_XRDC_MDA_W0_8_DFMT1_LK1_WIDTH (1U) 2134 #define RTU_XRDC_MDA_W0_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_LK1_MASK) 2135 2136 #define RTU_XRDC_MDA_W0_8_DFMT1_VLD_MASK (0x80000000U) 2137 #define RTU_XRDC_MDA_W0_8_DFMT1_VLD_SHIFT (31U) 2138 #define RTU_XRDC_MDA_W0_8_DFMT1_VLD_WIDTH (1U) 2139 #define RTU_XRDC_MDA_W0_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_8_DFMT1_VLD_MASK) 2140 /*! @} */ 2141 2142 /*! @name MDA_W1_8_DFMT1 - Master Domain Assignment */ 2143 /*! @{ */ 2144 2145 #define RTU_XRDC_MDA_W1_8_DFMT1_DID_MASK (0xFU) 2146 #define RTU_XRDC_MDA_W1_8_DFMT1_DID_SHIFT (0U) 2147 #define RTU_XRDC_MDA_W1_8_DFMT1_DID_WIDTH (4U) 2148 #define RTU_XRDC_MDA_W1_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_DID_MASK) 2149 2150 #define RTU_XRDC_MDA_W1_8_DFMT1_PA_MASK (0x30U) 2151 #define RTU_XRDC_MDA_W1_8_DFMT1_PA_SHIFT (4U) 2152 #define RTU_XRDC_MDA_W1_8_DFMT1_PA_WIDTH (2U) 2153 #define RTU_XRDC_MDA_W1_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_PA_MASK) 2154 2155 #define RTU_XRDC_MDA_W1_8_DFMT1_SA_MASK (0xC0U) 2156 #define RTU_XRDC_MDA_W1_8_DFMT1_SA_SHIFT (6U) 2157 #define RTU_XRDC_MDA_W1_8_DFMT1_SA_WIDTH (2U) 2158 #define RTU_XRDC_MDA_W1_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_SA_MASK) 2159 2160 #define RTU_XRDC_MDA_W1_8_DFMT1_DIDB_MASK (0x100U) 2161 #define RTU_XRDC_MDA_W1_8_DFMT1_DIDB_SHIFT (8U) 2162 #define RTU_XRDC_MDA_W1_8_DFMT1_DIDB_WIDTH (1U) 2163 #define RTU_XRDC_MDA_W1_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_DIDB_MASK) 2164 2165 #define RTU_XRDC_MDA_W1_8_DFMT1_LPID_MASK (0xF000000U) 2166 #define RTU_XRDC_MDA_W1_8_DFMT1_LPID_SHIFT (24U) 2167 #define RTU_XRDC_MDA_W1_8_DFMT1_LPID_WIDTH (4U) 2168 #define RTU_XRDC_MDA_W1_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_LPID_MASK) 2169 2170 #define RTU_XRDC_MDA_W1_8_DFMT1_LPE_MASK (0x10000000U) 2171 #define RTU_XRDC_MDA_W1_8_DFMT1_LPE_SHIFT (28U) 2172 #define RTU_XRDC_MDA_W1_8_DFMT1_LPE_WIDTH (1U) 2173 #define RTU_XRDC_MDA_W1_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_LPE_MASK) 2174 2175 #define RTU_XRDC_MDA_W1_8_DFMT1_DFMT_MASK (0x20000000U) 2176 #define RTU_XRDC_MDA_W1_8_DFMT1_DFMT_SHIFT (29U) 2177 #define RTU_XRDC_MDA_W1_8_DFMT1_DFMT_WIDTH (1U) 2178 #define RTU_XRDC_MDA_W1_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_DFMT_MASK) 2179 2180 #define RTU_XRDC_MDA_W1_8_DFMT1_LK1_MASK (0x40000000U) 2181 #define RTU_XRDC_MDA_W1_8_DFMT1_LK1_SHIFT (30U) 2182 #define RTU_XRDC_MDA_W1_8_DFMT1_LK1_WIDTH (1U) 2183 #define RTU_XRDC_MDA_W1_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_LK1_MASK) 2184 2185 #define RTU_XRDC_MDA_W1_8_DFMT1_VLD_MASK (0x80000000U) 2186 #define RTU_XRDC_MDA_W1_8_DFMT1_VLD_SHIFT (31U) 2187 #define RTU_XRDC_MDA_W1_8_DFMT1_VLD_WIDTH (1U) 2188 #define RTU_XRDC_MDA_W1_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_8_DFMT1_VLD_MASK) 2189 /*! @} */ 2190 2191 /*! @name MDA_W2_8_DFMT1 - Master Domain Assignment */ 2192 /*! @{ */ 2193 2194 #define RTU_XRDC_MDA_W2_8_DFMT1_DID_MASK (0xFU) 2195 #define RTU_XRDC_MDA_W2_8_DFMT1_DID_SHIFT (0U) 2196 #define RTU_XRDC_MDA_W2_8_DFMT1_DID_WIDTH (4U) 2197 #define RTU_XRDC_MDA_W2_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_DID_MASK) 2198 2199 #define RTU_XRDC_MDA_W2_8_DFMT1_PA_MASK (0x30U) 2200 #define RTU_XRDC_MDA_W2_8_DFMT1_PA_SHIFT (4U) 2201 #define RTU_XRDC_MDA_W2_8_DFMT1_PA_WIDTH (2U) 2202 #define RTU_XRDC_MDA_W2_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_PA_MASK) 2203 2204 #define RTU_XRDC_MDA_W2_8_DFMT1_SA_MASK (0xC0U) 2205 #define RTU_XRDC_MDA_W2_8_DFMT1_SA_SHIFT (6U) 2206 #define RTU_XRDC_MDA_W2_8_DFMT1_SA_WIDTH (2U) 2207 #define RTU_XRDC_MDA_W2_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_SA_MASK) 2208 2209 #define RTU_XRDC_MDA_W2_8_DFMT1_DIDB_MASK (0x100U) 2210 #define RTU_XRDC_MDA_W2_8_DFMT1_DIDB_SHIFT (8U) 2211 #define RTU_XRDC_MDA_W2_8_DFMT1_DIDB_WIDTH (1U) 2212 #define RTU_XRDC_MDA_W2_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_DIDB_MASK) 2213 2214 #define RTU_XRDC_MDA_W2_8_DFMT1_LPID_MASK (0xF000000U) 2215 #define RTU_XRDC_MDA_W2_8_DFMT1_LPID_SHIFT (24U) 2216 #define RTU_XRDC_MDA_W2_8_DFMT1_LPID_WIDTH (4U) 2217 #define RTU_XRDC_MDA_W2_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_LPID_MASK) 2218 2219 #define RTU_XRDC_MDA_W2_8_DFMT1_LPE_MASK (0x10000000U) 2220 #define RTU_XRDC_MDA_W2_8_DFMT1_LPE_SHIFT (28U) 2221 #define RTU_XRDC_MDA_W2_8_DFMT1_LPE_WIDTH (1U) 2222 #define RTU_XRDC_MDA_W2_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_LPE_MASK) 2223 2224 #define RTU_XRDC_MDA_W2_8_DFMT1_DFMT_MASK (0x20000000U) 2225 #define RTU_XRDC_MDA_W2_8_DFMT1_DFMT_SHIFT (29U) 2226 #define RTU_XRDC_MDA_W2_8_DFMT1_DFMT_WIDTH (1U) 2227 #define RTU_XRDC_MDA_W2_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_DFMT_MASK) 2228 2229 #define RTU_XRDC_MDA_W2_8_DFMT1_LK1_MASK (0x40000000U) 2230 #define RTU_XRDC_MDA_W2_8_DFMT1_LK1_SHIFT (30U) 2231 #define RTU_XRDC_MDA_W2_8_DFMT1_LK1_WIDTH (1U) 2232 #define RTU_XRDC_MDA_W2_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_LK1_MASK) 2233 2234 #define RTU_XRDC_MDA_W2_8_DFMT1_VLD_MASK (0x80000000U) 2235 #define RTU_XRDC_MDA_W2_8_DFMT1_VLD_SHIFT (31U) 2236 #define RTU_XRDC_MDA_W2_8_DFMT1_VLD_WIDTH (1U) 2237 #define RTU_XRDC_MDA_W2_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_8_DFMT1_VLD_MASK) 2238 /*! @} */ 2239 2240 /*! @name MDA_W3_8_DFMT1 - Master Domain Assignment */ 2241 /*! @{ */ 2242 2243 #define RTU_XRDC_MDA_W3_8_DFMT1_DID_MASK (0xFU) 2244 #define RTU_XRDC_MDA_W3_8_DFMT1_DID_SHIFT (0U) 2245 #define RTU_XRDC_MDA_W3_8_DFMT1_DID_WIDTH (4U) 2246 #define RTU_XRDC_MDA_W3_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_DID_MASK) 2247 2248 #define RTU_XRDC_MDA_W3_8_DFMT1_PA_MASK (0x30U) 2249 #define RTU_XRDC_MDA_W3_8_DFMT1_PA_SHIFT (4U) 2250 #define RTU_XRDC_MDA_W3_8_DFMT1_PA_WIDTH (2U) 2251 #define RTU_XRDC_MDA_W3_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_PA_MASK) 2252 2253 #define RTU_XRDC_MDA_W3_8_DFMT1_SA_MASK (0xC0U) 2254 #define RTU_XRDC_MDA_W3_8_DFMT1_SA_SHIFT (6U) 2255 #define RTU_XRDC_MDA_W3_8_DFMT1_SA_WIDTH (2U) 2256 #define RTU_XRDC_MDA_W3_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_SA_MASK) 2257 2258 #define RTU_XRDC_MDA_W3_8_DFMT1_DIDB_MASK (0x100U) 2259 #define RTU_XRDC_MDA_W3_8_DFMT1_DIDB_SHIFT (8U) 2260 #define RTU_XRDC_MDA_W3_8_DFMT1_DIDB_WIDTH (1U) 2261 #define RTU_XRDC_MDA_W3_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_DIDB_MASK) 2262 2263 #define RTU_XRDC_MDA_W3_8_DFMT1_LPID_MASK (0xF000000U) 2264 #define RTU_XRDC_MDA_W3_8_DFMT1_LPID_SHIFT (24U) 2265 #define RTU_XRDC_MDA_W3_8_DFMT1_LPID_WIDTH (4U) 2266 #define RTU_XRDC_MDA_W3_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_LPID_MASK) 2267 2268 #define RTU_XRDC_MDA_W3_8_DFMT1_LPE_MASK (0x10000000U) 2269 #define RTU_XRDC_MDA_W3_8_DFMT1_LPE_SHIFT (28U) 2270 #define RTU_XRDC_MDA_W3_8_DFMT1_LPE_WIDTH (1U) 2271 #define RTU_XRDC_MDA_W3_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_LPE_MASK) 2272 2273 #define RTU_XRDC_MDA_W3_8_DFMT1_DFMT_MASK (0x20000000U) 2274 #define RTU_XRDC_MDA_W3_8_DFMT1_DFMT_SHIFT (29U) 2275 #define RTU_XRDC_MDA_W3_8_DFMT1_DFMT_WIDTH (1U) 2276 #define RTU_XRDC_MDA_W3_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_DFMT_MASK) 2277 2278 #define RTU_XRDC_MDA_W3_8_DFMT1_LK1_MASK (0x40000000U) 2279 #define RTU_XRDC_MDA_W3_8_DFMT1_LK1_SHIFT (30U) 2280 #define RTU_XRDC_MDA_W3_8_DFMT1_LK1_WIDTH (1U) 2281 #define RTU_XRDC_MDA_W3_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_LK1_MASK) 2282 2283 #define RTU_XRDC_MDA_W3_8_DFMT1_VLD_MASK (0x80000000U) 2284 #define RTU_XRDC_MDA_W3_8_DFMT1_VLD_SHIFT (31U) 2285 #define RTU_XRDC_MDA_W3_8_DFMT1_VLD_WIDTH (1U) 2286 #define RTU_XRDC_MDA_W3_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_8_DFMT1_VLD_MASK) 2287 /*! @} */ 2288 2289 /*! @name MDA_W4_8_DFMT1 - Master Domain Assignment */ 2290 /*! @{ */ 2291 2292 #define RTU_XRDC_MDA_W4_8_DFMT1_DID_MASK (0xFU) 2293 #define RTU_XRDC_MDA_W4_8_DFMT1_DID_SHIFT (0U) 2294 #define RTU_XRDC_MDA_W4_8_DFMT1_DID_WIDTH (4U) 2295 #define RTU_XRDC_MDA_W4_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_DID_MASK) 2296 2297 #define RTU_XRDC_MDA_W4_8_DFMT1_PA_MASK (0x30U) 2298 #define RTU_XRDC_MDA_W4_8_DFMT1_PA_SHIFT (4U) 2299 #define RTU_XRDC_MDA_W4_8_DFMT1_PA_WIDTH (2U) 2300 #define RTU_XRDC_MDA_W4_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_PA_MASK) 2301 2302 #define RTU_XRDC_MDA_W4_8_DFMT1_SA_MASK (0xC0U) 2303 #define RTU_XRDC_MDA_W4_8_DFMT1_SA_SHIFT (6U) 2304 #define RTU_XRDC_MDA_W4_8_DFMT1_SA_WIDTH (2U) 2305 #define RTU_XRDC_MDA_W4_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_SA_MASK) 2306 2307 #define RTU_XRDC_MDA_W4_8_DFMT1_DIDB_MASK (0x100U) 2308 #define RTU_XRDC_MDA_W4_8_DFMT1_DIDB_SHIFT (8U) 2309 #define RTU_XRDC_MDA_W4_8_DFMT1_DIDB_WIDTH (1U) 2310 #define RTU_XRDC_MDA_W4_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_DIDB_MASK) 2311 2312 #define RTU_XRDC_MDA_W4_8_DFMT1_LPID_MASK (0xF000000U) 2313 #define RTU_XRDC_MDA_W4_8_DFMT1_LPID_SHIFT (24U) 2314 #define RTU_XRDC_MDA_W4_8_DFMT1_LPID_WIDTH (4U) 2315 #define RTU_XRDC_MDA_W4_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_LPID_MASK) 2316 2317 #define RTU_XRDC_MDA_W4_8_DFMT1_LPE_MASK (0x10000000U) 2318 #define RTU_XRDC_MDA_W4_8_DFMT1_LPE_SHIFT (28U) 2319 #define RTU_XRDC_MDA_W4_8_DFMT1_LPE_WIDTH (1U) 2320 #define RTU_XRDC_MDA_W4_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_LPE_MASK) 2321 2322 #define RTU_XRDC_MDA_W4_8_DFMT1_DFMT_MASK (0x20000000U) 2323 #define RTU_XRDC_MDA_W4_8_DFMT1_DFMT_SHIFT (29U) 2324 #define RTU_XRDC_MDA_W4_8_DFMT1_DFMT_WIDTH (1U) 2325 #define RTU_XRDC_MDA_W4_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_DFMT_MASK) 2326 2327 #define RTU_XRDC_MDA_W4_8_DFMT1_LK1_MASK (0x40000000U) 2328 #define RTU_XRDC_MDA_W4_8_DFMT1_LK1_SHIFT (30U) 2329 #define RTU_XRDC_MDA_W4_8_DFMT1_LK1_WIDTH (1U) 2330 #define RTU_XRDC_MDA_W4_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_LK1_MASK) 2331 2332 #define RTU_XRDC_MDA_W4_8_DFMT1_VLD_MASK (0x80000000U) 2333 #define RTU_XRDC_MDA_W4_8_DFMT1_VLD_SHIFT (31U) 2334 #define RTU_XRDC_MDA_W4_8_DFMT1_VLD_WIDTH (1U) 2335 #define RTU_XRDC_MDA_W4_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_8_DFMT1_VLD_MASK) 2336 /*! @} */ 2337 2338 /*! @name MDA_W5_8_DFMT1 - Master Domain Assignment */ 2339 /*! @{ */ 2340 2341 #define RTU_XRDC_MDA_W5_8_DFMT1_DID_MASK (0xFU) 2342 #define RTU_XRDC_MDA_W5_8_DFMT1_DID_SHIFT (0U) 2343 #define RTU_XRDC_MDA_W5_8_DFMT1_DID_WIDTH (4U) 2344 #define RTU_XRDC_MDA_W5_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_DID_MASK) 2345 2346 #define RTU_XRDC_MDA_W5_8_DFMT1_PA_MASK (0x30U) 2347 #define RTU_XRDC_MDA_W5_8_DFMT1_PA_SHIFT (4U) 2348 #define RTU_XRDC_MDA_W5_8_DFMT1_PA_WIDTH (2U) 2349 #define RTU_XRDC_MDA_W5_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_PA_MASK) 2350 2351 #define RTU_XRDC_MDA_W5_8_DFMT1_SA_MASK (0xC0U) 2352 #define RTU_XRDC_MDA_W5_8_DFMT1_SA_SHIFT (6U) 2353 #define RTU_XRDC_MDA_W5_8_DFMT1_SA_WIDTH (2U) 2354 #define RTU_XRDC_MDA_W5_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_SA_MASK) 2355 2356 #define RTU_XRDC_MDA_W5_8_DFMT1_DIDB_MASK (0x100U) 2357 #define RTU_XRDC_MDA_W5_8_DFMT1_DIDB_SHIFT (8U) 2358 #define RTU_XRDC_MDA_W5_8_DFMT1_DIDB_WIDTH (1U) 2359 #define RTU_XRDC_MDA_W5_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_DIDB_MASK) 2360 2361 #define RTU_XRDC_MDA_W5_8_DFMT1_LPID_MASK (0xF000000U) 2362 #define RTU_XRDC_MDA_W5_8_DFMT1_LPID_SHIFT (24U) 2363 #define RTU_XRDC_MDA_W5_8_DFMT1_LPID_WIDTH (4U) 2364 #define RTU_XRDC_MDA_W5_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_LPID_MASK) 2365 2366 #define RTU_XRDC_MDA_W5_8_DFMT1_LPE_MASK (0x10000000U) 2367 #define RTU_XRDC_MDA_W5_8_DFMT1_LPE_SHIFT (28U) 2368 #define RTU_XRDC_MDA_W5_8_DFMT1_LPE_WIDTH (1U) 2369 #define RTU_XRDC_MDA_W5_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_LPE_MASK) 2370 2371 #define RTU_XRDC_MDA_W5_8_DFMT1_DFMT_MASK (0x20000000U) 2372 #define RTU_XRDC_MDA_W5_8_DFMT1_DFMT_SHIFT (29U) 2373 #define RTU_XRDC_MDA_W5_8_DFMT1_DFMT_WIDTH (1U) 2374 #define RTU_XRDC_MDA_W5_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_DFMT_MASK) 2375 2376 #define RTU_XRDC_MDA_W5_8_DFMT1_LK1_MASK (0x40000000U) 2377 #define RTU_XRDC_MDA_W5_8_DFMT1_LK1_SHIFT (30U) 2378 #define RTU_XRDC_MDA_W5_8_DFMT1_LK1_WIDTH (1U) 2379 #define RTU_XRDC_MDA_W5_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_LK1_MASK) 2380 2381 #define RTU_XRDC_MDA_W5_8_DFMT1_VLD_MASK (0x80000000U) 2382 #define RTU_XRDC_MDA_W5_8_DFMT1_VLD_SHIFT (31U) 2383 #define RTU_XRDC_MDA_W5_8_DFMT1_VLD_WIDTH (1U) 2384 #define RTU_XRDC_MDA_W5_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_8_DFMT1_VLD_MASK) 2385 /*! @} */ 2386 2387 /*! @name MDA_W6_8_DFMT1 - Master Domain Assignment */ 2388 /*! @{ */ 2389 2390 #define RTU_XRDC_MDA_W6_8_DFMT1_DID_MASK (0xFU) 2391 #define RTU_XRDC_MDA_W6_8_DFMT1_DID_SHIFT (0U) 2392 #define RTU_XRDC_MDA_W6_8_DFMT1_DID_WIDTH (4U) 2393 #define RTU_XRDC_MDA_W6_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_DID_MASK) 2394 2395 #define RTU_XRDC_MDA_W6_8_DFMT1_PA_MASK (0x30U) 2396 #define RTU_XRDC_MDA_W6_8_DFMT1_PA_SHIFT (4U) 2397 #define RTU_XRDC_MDA_W6_8_DFMT1_PA_WIDTH (2U) 2398 #define RTU_XRDC_MDA_W6_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_PA_MASK) 2399 2400 #define RTU_XRDC_MDA_W6_8_DFMT1_SA_MASK (0xC0U) 2401 #define RTU_XRDC_MDA_W6_8_DFMT1_SA_SHIFT (6U) 2402 #define RTU_XRDC_MDA_W6_8_DFMT1_SA_WIDTH (2U) 2403 #define RTU_XRDC_MDA_W6_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_SA_MASK) 2404 2405 #define RTU_XRDC_MDA_W6_8_DFMT1_DIDB_MASK (0x100U) 2406 #define RTU_XRDC_MDA_W6_8_DFMT1_DIDB_SHIFT (8U) 2407 #define RTU_XRDC_MDA_W6_8_DFMT1_DIDB_WIDTH (1U) 2408 #define RTU_XRDC_MDA_W6_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_DIDB_MASK) 2409 2410 #define RTU_XRDC_MDA_W6_8_DFMT1_LPID_MASK (0xF000000U) 2411 #define RTU_XRDC_MDA_W6_8_DFMT1_LPID_SHIFT (24U) 2412 #define RTU_XRDC_MDA_W6_8_DFMT1_LPID_WIDTH (4U) 2413 #define RTU_XRDC_MDA_W6_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_LPID_MASK) 2414 2415 #define RTU_XRDC_MDA_W6_8_DFMT1_LPE_MASK (0x10000000U) 2416 #define RTU_XRDC_MDA_W6_8_DFMT1_LPE_SHIFT (28U) 2417 #define RTU_XRDC_MDA_W6_8_DFMT1_LPE_WIDTH (1U) 2418 #define RTU_XRDC_MDA_W6_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_LPE_MASK) 2419 2420 #define RTU_XRDC_MDA_W6_8_DFMT1_DFMT_MASK (0x20000000U) 2421 #define RTU_XRDC_MDA_W6_8_DFMT1_DFMT_SHIFT (29U) 2422 #define RTU_XRDC_MDA_W6_8_DFMT1_DFMT_WIDTH (1U) 2423 #define RTU_XRDC_MDA_W6_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_DFMT_MASK) 2424 2425 #define RTU_XRDC_MDA_W6_8_DFMT1_LK1_MASK (0x40000000U) 2426 #define RTU_XRDC_MDA_W6_8_DFMT1_LK1_SHIFT (30U) 2427 #define RTU_XRDC_MDA_W6_8_DFMT1_LK1_WIDTH (1U) 2428 #define RTU_XRDC_MDA_W6_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_LK1_MASK) 2429 2430 #define RTU_XRDC_MDA_W6_8_DFMT1_VLD_MASK (0x80000000U) 2431 #define RTU_XRDC_MDA_W6_8_DFMT1_VLD_SHIFT (31U) 2432 #define RTU_XRDC_MDA_W6_8_DFMT1_VLD_WIDTH (1U) 2433 #define RTU_XRDC_MDA_W6_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_8_DFMT1_VLD_MASK) 2434 /*! @} */ 2435 2436 /*! @name MDA_W7_8_DFMT1 - Master Domain Assignment */ 2437 /*! @{ */ 2438 2439 #define RTU_XRDC_MDA_W7_8_DFMT1_DID_MASK (0xFU) 2440 #define RTU_XRDC_MDA_W7_8_DFMT1_DID_SHIFT (0U) 2441 #define RTU_XRDC_MDA_W7_8_DFMT1_DID_WIDTH (4U) 2442 #define RTU_XRDC_MDA_W7_8_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_DID_MASK) 2443 2444 #define RTU_XRDC_MDA_W7_8_DFMT1_PA_MASK (0x30U) 2445 #define RTU_XRDC_MDA_W7_8_DFMT1_PA_SHIFT (4U) 2446 #define RTU_XRDC_MDA_W7_8_DFMT1_PA_WIDTH (2U) 2447 #define RTU_XRDC_MDA_W7_8_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_PA_MASK) 2448 2449 #define RTU_XRDC_MDA_W7_8_DFMT1_SA_MASK (0xC0U) 2450 #define RTU_XRDC_MDA_W7_8_DFMT1_SA_SHIFT (6U) 2451 #define RTU_XRDC_MDA_W7_8_DFMT1_SA_WIDTH (2U) 2452 #define RTU_XRDC_MDA_W7_8_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_SA_MASK) 2453 2454 #define RTU_XRDC_MDA_W7_8_DFMT1_DIDB_MASK (0x100U) 2455 #define RTU_XRDC_MDA_W7_8_DFMT1_DIDB_SHIFT (8U) 2456 #define RTU_XRDC_MDA_W7_8_DFMT1_DIDB_WIDTH (1U) 2457 #define RTU_XRDC_MDA_W7_8_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_DIDB_MASK) 2458 2459 #define RTU_XRDC_MDA_W7_8_DFMT1_LPID_MASK (0xF000000U) 2460 #define RTU_XRDC_MDA_W7_8_DFMT1_LPID_SHIFT (24U) 2461 #define RTU_XRDC_MDA_W7_8_DFMT1_LPID_WIDTH (4U) 2462 #define RTU_XRDC_MDA_W7_8_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_LPID_MASK) 2463 2464 #define RTU_XRDC_MDA_W7_8_DFMT1_LPE_MASK (0x10000000U) 2465 #define RTU_XRDC_MDA_W7_8_DFMT1_LPE_SHIFT (28U) 2466 #define RTU_XRDC_MDA_W7_8_DFMT1_LPE_WIDTH (1U) 2467 #define RTU_XRDC_MDA_W7_8_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_LPE_MASK) 2468 2469 #define RTU_XRDC_MDA_W7_8_DFMT1_DFMT_MASK (0x20000000U) 2470 #define RTU_XRDC_MDA_W7_8_DFMT1_DFMT_SHIFT (29U) 2471 #define RTU_XRDC_MDA_W7_8_DFMT1_DFMT_WIDTH (1U) 2472 #define RTU_XRDC_MDA_W7_8_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_DFMT_MASK) 2473 2474 #define RTU_XRDC_MDA_W7_8_DFMT1_LK1_MASK (0x40000000U) 2475 #define RTU_XRDC_MDA_W7_8_DFMT1_LK1_SHIFT (30U) 2476 #define RTU_XRDC_MDA_W7_8_DFMT1_LK1_WIDTH (1U) 2477 #define RTU_XRDC_MDA_W7_8_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_LK1_MASK) 2478 2479 #define RTU_XRDC_MDA_W7_8_DFMT1_VLD_MASK (0x80000000U) 2480 #define RTU_XRDC_MDA_W7_8_DFMT1_VLD_SHIFT (31U) 2481 #define RTU_XRDC_MDA_W7_8_DFMT1_VLD_WIDTH (1U) 2482 #define RTU_XRDC_MDA_W7_8_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_8_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_8_DFMT1_VLD_MASK) 2483 /*! @} */ 2484 2485 /*! @name MDA_W0_9_DFMT1 - Master Domain Assignment */ 2486 /*! @{ */ 2487 2488 #define RTU_XRDC_MDA_W0_9_DFMT1_DID_MASK (0xFU) 2489 #define RTU_XRDC_MDA_W0_9_DFMT1_DID_SHIFT (0U) 2490 #define RTU_XRDC_MDA_W0_9_DFMT1_DID_WIDTH (4U) 2491 #define RTU_XRDC_MDA_W0_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_DID_MASK) 2492 2493 #define RTU_XRDC_MDA_W0_9_DFMT1_PA_MASK (0x30U) 2494 #define RTU_XRDC_MDA_W0_9_DFMT1_PA_SHIFT (4U) 2495 #define RTU_XRDC_MDA_W0_9_DFMT1_PA_WIDTH (2U) 2496 #define RTU_XRDC_MDA_W0_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_PA_MASK) 2497 2498 #define RTU_XRDC_MDA_W0_9_DFMT1_SA_MASK (0xC0U) 2499 #define RTU_XRDC_MDA_W0_9_DFMT1_SA_SHIFT (6U) 2500 #define RTU_XRDC_MDA_W0_9_DFMT1_SA_WIDTH (2U) 2501 #define RTU_XRDC_MDA_W0_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_SA_MASK) 2502 2503 #define RTU_XRDC_MDA_W0_9_DFMT1_DIDB_MASK (0x100U) 2504 #define RTU_XRDC_MDA_W0_9_DFMT1_DIDB_SHIFT (8U) 2505 #define RTU_XRDC_MDA_W0_9_DFMT1_DIDB_WIDTH (1U) 2506 #define RTU_XRDC_MDA_W0_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_DIDB_MASK) 2507 2508 #define RTU_XRDC_MDA_W0_9_DFMT1_LPID_MASK (0xF000000U) 2509 #define RTU_XRDC_MDA_W0_9_DFMT1_LPID_SHIFT (24U) 2510 #define RTU_XRDC_MDA_W0_9_DFMT1_LPID_WIDTH (4U) 2511 #define RTU_XRDC_MDA_W0_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_LPID_MASK) 2512 2513 #define RTU_XRDC_MDA_W0_9_DFMT1_LPE_MASK (0x10000000U) 2514 #define RTU_XRDC_MDA_W0_9_DFMT1_LPE_SHIFT (28U) 2515 #define RTU_XRDC_MDA_W0_9_DFMT1_LPE_WIDTH (1U) 2516 #define RTU_XRDC_MDA_W0_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_LPE_MASK) 2517 2518 #define RTU_XRDC_MDA_W0_9_DFMT1_DFMT_MASK (0x20000000U) 2519 #define RTU_XRDC_MDA_W0_9_DFMT1_DFMT_SHIFT (29U) 2520 #define RTU_XRDC_MDA_W0_9_DFMT1_DFMT_WIDTH (1U) 2521 #define RTU_XRDC_MDA_W0_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_DFMT_MASK) 2522 2523 #define RTU_XRDC_MDA_W0_9_DFMT1_LK1_MASK (0x40000000U) 2524 #define RTU_XRDC_MDA_W0_9_DFMT1_LK1_SHIFT (30U) 2525 #define RTU_XRDC_MDA_W0_9_DFMT1_LK1_WIDTH (1U) 2526 #define RTU_XRDC_MDA_W0_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_LK1_MASK) 2527 2528 #define RTU_XRDC_MDA_W0_9_DFMT1_VLD_MASK (0x80000000U) 2529 #define RTU_XRDC_MDA_W0_9_DFMT1_VLD_SHIFT (31U) 2530 #define RTU_XRDC_MDA_W0_9_DFMT1_VLD_WIDTH (1U) 2531 #define RTU_XRDC_MDA_W0_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_9_DFMT1_VLD_MASK) 2532 /*! @} */ 2533 2534 /*! @name MDA_W1_9_DFMT1 - Master Domain Assignment */ 2535 /*! @{ */ 2536 2537 #define RTU_XRDC_MDA_W1_9_DFMT1_DID_MASK (0xFU) 2538 #define RTU_XRDC_MDA_W1_9_DFMT1_DID_SHIFT (0U) 2539 #define RTU_XRDC_MDA_W1_9_DFMT1_DID_WIDTH (4U) 2540 #define RTU_XRDC_MDA_W1_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_DID_MASK) 2541 2542 #define RTU_XRDC_MDA_W1_9_DFMT1_PA_MASK (0x30U) 2543 #define RTU_XRDC_MDA_W1_9_DFMT1_PA_SHIFT (4U) 2544 #define RTU_XRDC_MDA_W1_9_DFMT1_PA_WIDTH (2U) 2545 #define RTU_XRDC_MDA_W1_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_PA_MASK) 2546 2547 #define RTU_XRDC_MDA_W1_9_DFMT1_SA_MASK (0xC0U) 2548 #define RTU_XRDC_MDA_W1_9_DFMT1_SA_SHIFT (6U) 2549 #define RTU_XRDC_MDA_W1_9_DFMT1_SA_WIDTH (2U) 2550 #define RTU_XRDC_MDA_W1_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_SA_MASK) 2551 2552 #define RTU_XRDC_MDA_W1_9_DFMT1_DIDB_MASK (0x100U) 2553 #define RTU_XRDC_MDA_W1_9_DFMT1_DIDB_SHIFT (8U) 2554 #define RTU_XRDC_MDA_W1_9_DFMT1_DIDB_WIDTH (1U) 2555 #define RTU_XRDC_MDA_W1_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_DIDB_MASK) 2556 2557 #define RTU_XRDC_MDA_W1_9_DFMT1_LPID_MASK (0xF000000U) 2558 #define RTU_XRDC_MDA_W1_9_DFMT1_LPID_SHIFT (24U) 2559 #define RTU_XRDC_MDA_W1_9_DFMT1_LPID_WIDTH (4U) 2560 #define RTU_XRDC_MDA_W1_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_LPID_MASK) 2561 2562 #define RTU_XRDC_MDA_W1_9_DFMT1_LPE_MASK (0x10000000U) 2563 #define RTU_XRDC_MDA_W1_9_DFMT1_LPE_SHIFT (28U) 2564 #define RTU_XRDC_MDA_W1_9_DFMT1_LPE_WIDTH (1U) 2565 #define RTU_XRDC_MDA_W1_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_LPE_MASK) 2566 2567 #define RTU_XRDC_MDA_W1_9_DFMT1_DFMT_MASK (0x20000000U) 2568 #define RTU_XRDC_MDA_W1_9_DFMT1_DFMT_SHIFT (29U) 2569 #define RTU_XRDC_MDA_W1_9_DFMT1_DFMT_WIDTH (1U) 2570 #define RTU_XRDC_MDA_W1_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_DFMT_MASK) 2571 2572 #define RTU_XRDC_MDA_W1_9_DFMT1_LK1_MASK (0x40000000U) 2573 #define RTU_XRDC_MDA_W1_9_DFMT1_LK1_SHIFT (30U) 2574 #define RTU_XRDC_MDA_W1_9_DFMT1_LK1_WIDTH (1U) 2575 #define RTU_XRDC_MDA_W1_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_LK1_MASK) 2576 2577 #define RTU_XRDC_MDA_W1_9_DFMT1_VLD_MASK (0x80000000U) 2578 #define RTU_XRDC_MDA_W1_9_DFMT1_VLD_SHIFT (31U) 2579 #define RTU_XRDC_MDA_W1_9_DFMT1_VLD_WIDTH (1U) 2580 #define RTU_XRDC_MDA_W1_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_9_DFMT1_VLD_MASK) 2581 /*! @} */ 2582 2583 /*! @name MDA_W2_9_DFMT1 - Master Domain Assignment */ 2584 /*! @{ */ 2585 2586 #define RTU_XRDC_MDA_W2_9_DFMT1_DID_MASK (0xFU) 2587 #define RTU_XRDC_MDA_W2_9_DFMT1_DID_SHIFT (0U) 2588 #define RTU_XRDC_MDA_W2_9_DFMT1_DID_WIDTH (4U) 2589 #define RTU_XRDC_MDA_W2_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_DID_MASK) 2590 2591 #define RTU_XRDC_MDA_W2_9_DFMT1_PA_MASK (0x30U) 2592 #define RTU_XRDC_MDA_W2_9_DFMT1_PA_SHIFT (4U) 2593 #define RTU_XRDC_MDA_W2_9_DFMT1_PA_WIDTH (2U) 2594 #define RTU_XRDC_MDA_W2_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_PA_MASK) 2595 2596 #define RTU_XRDC_MDA_W2_9_DFMT1_SA_MASK (0xC0U) 2597 #define RTU_XRDC_MDA_W2_9_DFMT1_SA_SHIFT (6U) 2598 #define RTU_XRDC_MDA_W2_9_DFMT1_SA_WIDTH (2U) 2599 #define RTU_XRDC_MDA_W2_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_SA_MASK) 2600 2601 #define RTU_XRDC_MDA_W2_9_DFMT1_DIDB_MASK (0x100U) 2602 #define RTU_XRDC_MDA_W2_9_DFMT1_DIDB_SHIFT (8U) 2603 #define RTU_XRDC_MDA_W2_9_DFMT1_DIDB_WIDTH (1U) 2604 #define RTU_XRDC_MDA_W2_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_DIDB_MASK) 2605 2606 #define RTU_XRDC_MDA_W2_9_DFMT1_LPID_MASK (0xF000000U) 2607 #define RTU_XRDC_MDA_W2_9_DFMT1_LPID_SHIFT (24U) 2608 #define RTU_XRDC_MDA_W2_9_DFMT1_LPID_WIDTH (4U) 2609 #define RTU_XRDC_MDA_W2_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_LPID_MASK) 2610 2611 #define RTU_XRDC_MDA_W2_9_DFMT1_LPE_MASK (0x10000000U) 2612 #define RTU_XRDC_MDA_W2_9_DFMT1_LPE_SHIFT (28U) 2613 #define RTU_XRDC_MDA_W2_9_DFMT1_LPE_WIDTH (1U) 2614 #define RTU_XRDC_MDA_W2_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_LPE_MASK) 2615 2616 #define RTU_XRDC_MDA_W2_9_DFMT1_DFMT_MASK (0x20000000U) 2617 #define RTU_XRDC_MDA_W2_9_DFMT1_DFMT_SHIFT (29U) 2618 #define RTU_XRDC_MDA_W2_9_DFMT1_DFMT_WIDTH (1U) 2619 #define RTU_XRDC_MDA_W2_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_DFMT_MASK) 2620 2621 #define RTU_XRDC_MDA_W2_9_DFMT1_LK1_MASK (0x40000000U) 2622 #define RTU_XRDC_MDA_W2_9_DFMT1_LK1_SHIFT (30U) 2623 #define RTU_XRDC_MDA_W2_9_DFMT1_LK1_WIDTH (1U) 2624 #define RTU_XRDC_MDA_W2_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_LK1_MASK) 2625 2626 #define RTU_XRDC_MDA_W2_9_DFMT1_VLD_MASK (0x80000000U) 2627 #define RTU_XRDC_MDA_W2_9_DFMT1_VLD_SHIFT (31U) 2628 #define RTU_XRDC_MDA_W2_9_DFMT1_VLD_WIDTH (1U) 2629 #define RTU_XRDC_MDA_W2_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_9_DFMT1_VLD_MASK) 2630 /*! @} */ 2631 2632 /*! @name MDA_W3_9_DFMT1 - Master Domain Assignment */ 2633 /*! @{ */ 2634 2635 #define RTU_XRDC_MDA_W3_9_DFMT1_DID_MASK (0xFU) 2636 #define RTU_XRDC_MDA_W3_9_DFMT1_DID_SHIFT (0U) 2637 #define RTU_XRDC_MDA_W3_9_DFMT1_DID_WIDTH (4U) 2638 #define RTU_XRDC_MDA_W3_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_DID_MASK) 2639 2640 #define RTU_XRDC_MDA_W3_9_DFMT1_PA_MASK (0x30U) 2641 #define RTU_XRDC_MDA_W3_9_DFMT1_PA_SHIFT (4U) 2642 #define RTU_XRDC_MDA_W3_9_DFMT1_PA_WIDTH (2U) 2643 #define RTU_XRDC_MDA_W3_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_PA_MASK) 2644 2645 #define RTU_XRDC_MDA_W3_9_DFMT1_SA_MASK (0xC0U) 2646 #define RTU_XRDC_MDA_W3_9_DFMT1_SA_SHIFT (6U) 2647 #define RTU_XRDC_MDA_W3_9_DFMT1_SA_WIDTH (2U) 2648 #define RTU_XRDC_MDA_W3_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_SA_MASK) 2649 2650 #define RTU_XRDC_MDA_W3_9_DFMT1_DIDB_MASK (0x100U) 2651 #define RTU_XRDC_MDA_W3_9_DFMT1_DIDB_SHIFT (8U) 2652 #define RTU_XRDC_MDA_W3_9_DFMT1_DIDB_WIDTH (1U) 2653 #define RTU_XRDC_MDA_W3_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_DIDB_MASK) 2654 2655 #define RTU_XRDC_MDA_W3_9_DFMT1_LPID_MASK (0xF000000U) 2656 #define RTU_XRDC_MDA_W3_9_DFMT1_LPID_SHIFT (24U) 2657 #define RTU_XRDC_MDA_W3_9_DFMT1_LPID_WIDTH (4U) 2658 #define RTU_XRDC_MDA_W3_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_LPID_MASK) 2659 2660 #define RTU_XRDC_MDA_W3_9_DFMT1_LPE_MASK (0x10000000U) 2661 #define RTU_XRDC_MDA_W3_9_DFMT1_LPE_SHIFT (28U) 2662 #define RTU_XRDC_MDA_W3_9_DFMT1_LPE_WIDTH (1U) 2663 #define RTU_XRDC_MDA_W3_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_LPE_MASK) 2664 2665 #define RTU_XRDC_MDA_W3_9_DFMT1_DFMT_MASK (0x20000000U) 2666 #define RTU_XRDC_MDA_W3_9_DFMT1_DFMT_SHIFT (29U) 2667 #define RTU_XRDC_MDA_W3_9_DFMT1_DFMT_WIDTH (1U) 2668 #define RTU_XRDC_MDA_W3_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_DFMT_MASK) 2669 2670 #define RTU_XRDC_MDA_W3_9_DFMT1_LK1_MASK (0x40000000U) 2671 #define RTU_XRDC_MDA_W3_9_DFMT1_LK1_SHIFT (30U) 2672 #define RTU_XRDC_MDA_W3_9_DFMT1_LK1_WIDTH (1U) 2673 #define RTU_XRDC_MDA_W3_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_LK1_MASK) 2674 2675 #define RTU_XRDC_MDA_W3_9_DFMT1_VLD_MASK (0x80000000U) 2676 #define RTU_XRDC_MDA_W3_9_DFMT1_VLD_SHIFT (31U) 2677 #define RTU_XRDC_MDA_W3_9_DFMT1_VLD_WIDTH (1U) 2678 #define RTU_XRDC_MDA_W3_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_9_DFMT1_VLD_MASK) 2679 /*! @} */ 2680 2681 /*! @name MDA_W4_9_DFMT1 - Master Domain Assignment */ 2682 /*! @{ */ 2683 2684 #define RTU_XRDC_MDA_W4_9_DFMT1_DID_MASK (0xFU) 2685 #define RTU_XRDC_MDA_W4_9_DFMT1_DID_SHIFT (0U) 2686 #define RTU_XRDC_MDA_W4_9_DFMT1_DID_WIDTH (4U) 2687 #define RTU_XRDC_MDA_W4_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_DID_MASK) 2688 2689 #define RTU_XRDC_MDA_W4_9_DFMT1_PA_MASK (0x30U) 2690 #define RTU_XRDC_MDA_W4_9_DFMT1_PA_SHIFT (4U) 2691 #define RTU_XRDC_MDA_W4_9_DFMT1_PA_WIDTH (2U) 2692 #define RTU_XRDC_MDA_W4_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_PA_MASK) 2693 2694 #define RTU_XRDC_MDA_W4_9_DFMT1_SA_MASK (0xC0U) 2695 #define RTU_XRDC_MDA_W4_9_DFMT1_SA_SHIFT (6U) 2696 #define RTU_XRDC_MDA_W4_9_DFMT1_SA_WIDTH (2U) 2697 #define RTU_XRDC_MDA_W4_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_SA_MASK) 2698 2699 #define RTU_XRDC_MDA_W4_9_DFMT1_DIDB_MASK (0x100U) 2700 #define RTU_XRDC_MDA_W4_9_DFMT1_DIDB_SHIFT (8U) 2701 #define RTU_XRDC_MDA_W4_9_DFMT1_DIDB_WIDTH (1U) 2702 #define RTU_XRDC_MDA_W4_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_DIDB_MASK) 2703 2704 #define RTU_XRDC_MDA_W4_9_DFMT1_LPID_MASK (0xF000000U) 2705 #define RTU_XRDC_MDA_W4_9_DFMT1_LPID_SHIFT (24U) 2706 #define RTU_XRDC_MDA_W4_9_DFMT1_LPID_WIDTH (4U) 2707 #define RTU_XRDC_MDA_W4_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_LPID_MASK) 2708 2709 #define RTU_XRDC_MDA_W4_9_DFMT1_LPE_MASK (0x10000000U) 2710 #define RTU_XRDC_MDA_W4_9_DFMT1_LPE_SHIFT (28U) 2711 #define RTU_XRDC_MDA_W4_9_DFMT1_LPE_WIDTH (1U) 2712 #define RTU_XRDC_MDA_W4_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_LPE_MASK) 2713 2714 #define RTU_XRDC_MDA_W4_9_DFMT1_DFMT_MASK (0x20000000U) 2715 #define RTU_XRDC_MDA_W4_9_DFMT1_DFMT_SHIFT (29U) 2716 #define RTU_XRDC_MDA_W4_9_DFMT1_DFMT_WIDTH (1U) 2717 #define RTU_XRDC_MDA_W4_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_DFMT_MASK) 2718 2719 #define RTU_XRDC_MDA_W4_9_DFMT1_LK1_MASK (0x40000000U) 2720 #define RTU_XRDC_MDA_W4_9_DFMT1_LK1_SHIFT (30U) 2721 #define RTU_XRDC_MDA_W4_9_DFMT1_LK1_WIDTH (1U) 2722 #define RTU_XRDC_MDA_W4_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_LK1_MASK) 2723 2724 #define RTU_XRDC_MDA_W4_9_DFMT1_VLD_MASK (0x80000000U) 2725 #define RTU_XRDC_MDA_W4_9_DFMT1_VLD_SHIFT (31U) 2726 #define RTU_XRDC_MDA_W4_9_DFMT1_VLD_WIDTH (1U) 2727 #define RTU_XRDC_MDA_W4_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_9_DFMT1_VLD_MASK) 2728 /*! @} */ 2729 2730 /*! @name MDA_W5_9_DFMT1 - Master Domain Assignment */ 2731 /*! @{ */ 2732 2733 #define RTU_XRDC_MDA_W5_9_DFMT1_DID_MASK (0xFU) 2734 #define RTU_XRDC_MDA_W5_9_DFMT1_DID_SHIFT (0U) 2735 #define RTU_XRDC_MDA_W5_9_DFMT1_DID_WIDTH (4U) 2736 #define RTU_XRDC_MDA_W5_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_DID_MASK) 2737 2738 #define RTU_XRDC_MDA_W5_9_DFMT1_PA_MASK (0x30U) 2739 #define RTU_XRDC_MDA_W5_9_DFMT1_PA_SHIFT (4U) 2740 #define RTU_XRDC_MDA_W5_9_DFMT1_PA_WIDTH (2U) 2741 #define RTU_XRDC_MDA_W5_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_PA_MASK) 2742 2743 #define RTU_XRDC_MDA_W5_9_DFMT1_SA_MASK (0xC0U) 2744 #define RTU_XRDC_MDA_W5_9_DFMT1_SA_SHIFT (6U) 2745 #define RTU_XRDC_MDA_W5_9_DFMT1_SA_WIDTH (2U) 2746 #define RTU_XRDC_MDA_W5_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_SA_MASK) 2747 2748 #define RTU_XRDC_MDA_W5_9_DFMT1_DIDB_MASK (0x100U) 2749 #define RTU_XRDC_MDA_W5_9_DFMT1_DIDB_SHIFT (8U) 2750 #define RTU_XRDC_MDA_W5_9_DFMT1_DIDB_WIDTH (1U) 2751 #define RTU_XRDC_MDA_W5_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_DIDB_MASK) 2752 2753 #define RTU_XRDC_MDA_W5_9_DFMT1_LPID_MASK (0xF000000U) 2754 #define RTU_XRDC_MDA_W5_9_DFMT1_LPID_SHIFT (24U) 2755 #define RTU_XRDC_MDA_W5_9_DFMT1_LPID_WIDTH (4U) 2756 #define RTU_XRDC_MDA_W5_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_LPID_MASK) 2757 2758 #define RTU_XRDC_MDA_W5_9_DFMT1_LPE_MASK (0x10000000U) 2759 #define RTU_XRDC_MDA_W5_9_DFMT1_LPE_SHIFT (28U) 2760 #define RTU_XRDC_MDA_W5_9_DFMT1_LPE_WIDTH (1U) 2761 #define RTU_XRDC_MDA_W5_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_LPE_MASK) 2762 2763 #define RTU_XRDC_MDA_W5_9_DFMT1_DFMT_MASK (0x20000000U) 2764 #define RTU_XRDC_MDA_W5_9_DFMT1_DFMT_SHIFT (29U) 2765 #define RTU_XRDC_MDA_W5_9_DFMT1_DFMT_WIDTH (1U) 2766 #define RTU_XRDC_MDA_W5_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_DFMT_MASK) 2767 2768 #define RTU_XRDC_MDA_W5_9_DFMT1_LK1_MASK (0x40000000U) 2769 #define RTU_XRDC_MDA_W5_9_DFMT1_LK1_SHIFT (30U) 2770 #define RTU_XRDC_MDA_W5_9_DFMT1_LK1_WIDTH (1U) 2771 #define RTU_XRDC_MDA_W5_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_LK1_MASK) 2772 2773 #define RTU_XRDC_MDA_W5_9_DFMT1_VLD_MASK (0x80000000U) 2774 #define RTU_XRDC_MDA_W5_9_DFMT1_VLD_SHIFT (31U) 2775 #define RTU_XRDC_MDA_W5_9_DFMT1_VLD_WIDTH (1U) 2776 #define RTU_XRDC_MDA_W5_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_9_DFMT1_VLD_MASK) 2777 /*! @} */ 2778 2779 /*! @name MDA_W6_9_DFMT1 - Master Domain Assignment */ 2780 /*! @{ */ 2781 2782 #define RTU_XRDC_MDA_W6_9_DFMT1_DID_MASK (0xFU) 2783 #define RTU_XRDC_MDA_W6_9_DFMT1_DID_SHIFT (0U) 2784 #define RTU_XRDC_MDA_W6_9_DFMT1_DID_WIDTH (4U) 2785 #define RTU_XRDC_MDA_W6_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_DID_MASK) 2786 2787 #define RTU_XRDC_MDA_W6_9_DFMT1_PA_MASK (0x30U) 2788 #define RTU_XRDC_MDA_W6_9_DFMT1_PA_SHIFT (4U) 2789 #define RTU_XRDC_MDA_W6_9_DFMT1_PA_WIDTH (2U) 2790 #define RTU_XRDC_MDA_W6_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_PA_MASK) 2791 2792 #define RTU_XRDC_MDA_W6_9_DFMT1_SA_MASK (0xC0U) 2793 #define RTU_XRDC_MDA_W6_9_DFMT1_SA_SHIFT (6U) 2794 #define RTU_XRDC_MDA_W6_9_DFMT1_SA_WIDTH (2U) 2795 #define RTU_XRDC_MDA_W6_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_SA_MASK) 2796 2797 #define RTU_XRDC_MDA_W6_9_DFMT1_DIDB_MASK (0x100U) 2798 #define RTU_XRDC_MDA_W6_9_DFMT1_DIDB_SHIFT (8U) 2799 #define RTU_XRDC_MDA_W6_9_DFMT1_DIDB_WIDTH (1U) 2800 #define RTU_XRDC_MDA_W6_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_DIDB_MASK) 2801 2802 #define RTU_XRDC_MDA_W6_9_DFMT1_LPID_MASK (0xF000000U) 2803 #define RTU_XRDC_MDA_W6_9_DFMT1_LPID_SHIFT (24U) 2804 #define RTU_XRDC_MDA_W6_9_DFMT1_LPID_WIDTH (4U) 2805 #define RTU_XRDC_MDA_W6_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_LPID_MASK) 2806 2807 #define RTU_XRDC_MDA_W6_9_DFMT1_LPE_MASK (0x10000000U) 2808 #define RTU_XRDC_MDA_W6_9_DFMT1_LPE_SHIFT (28U) 2809 #define RTU_XRDC_MDA_W6_9_DFMT1_LPE_WIDTH (1U) 2810 #define RTU_XRDC_MDA_W6_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_LPE_MASK) 2811 2812 #define RTU_XRDC_MDA_W6_9_DFMT1_DFMT_MASK (0x20000000U) 2813 #define RTU_XRDC_MDA_W6_9_DFMT1_DFMT_SHIFT (29U) 2814 #define RTU_XRDC_MDA_W6_9_DFMT1_DFMT_WIDTH (1U) 2815 #define RTU_XRDC_MDA_W6_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_DFMT_MASK) 2816 2817 #define RTU_XRDC_MDA_W6_9_DFMT1_LK1_MASK (0x40000000U) 2818 #define RTU_XRDC_MDA_W6_9_DFMT1_LK1_SHIFT (30U) 2819 #define RTU_XRDC_MDA_W6_9_DFMT1_LK1_WIDTH (1U) 2820 #define RTU_XRDC_MDA_W6_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_LK1_MASK) 2821 2822 #define RTU_XRDC_MDA_W6_9_DFMT1_VLD_MASK (0x80000000U) 2823 #define RTU_XRDC_MDA_W6_9_DFMT1_VLD_SHIFT (31U) 2824 #define RTU_XRDC_MDA_W6_9_DFMT1_VLD_WIDTH (1U) 2825 #define RTU_XRDC_MDA_W6_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_9_DFMT1_VLD_MASK) 2826 /*! @} */ 2827 2828 /*! @name MDA_W7_9_DFMT1 - Master Domain Assignment */ 2829 /*! @{ */ 2830 2831 #define RTU_XRDC_MDA_W7_9_DFMT1_DID_MASK (0xFU) 2832 #define RTU_XRDC_MDA_W7_9_DFMT1_DID_SHIFT (0U) 2833 #define RTU_XRDC_MDA_W7_9_DFMT1_DID_WIDTH (4U) 2834 #define RTU_XRDC_MDA_W7_9_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_DID_MASK) 2835 2836 #define RTU_XRDC_MDA_W7_9_DFMT1_PA_MASK (0x30U) 2837 #define RTU_XRDC_MDA_W7_9_DFMT1_PA_SHIFT (4U) 2838 #define RTU_XRDC_MDA_W7_9_DFMT1_PA_WIDTH (2U) 2839 #define RTU_XRDC_MDA_W7_9_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_PA_MASK) 2840 2841 #define RTU_XRDC_MDA_W7_9_DFMT1_SA_MASK (0xC0U) 2842 #define RTU_XRDC_MDA_W7_9_DFMT1_SA_SHIFT (6U) 2843 #define RTU_XRDC_MDA_W7_9_DFMT1_SA_WIDTH (2U) 2844 #define RTU_XRDC_MDA_W7_9_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_SA_MASK) 2845 2846 #define RTU_XRDC_MDA_W7_9_DFMT1_DIDB_MASK (0x100U) 2847 #define RTU_XRDC_MDA_W7_9_DFMT1_DIDB_SHIFT (8U) 2848 #define RTU_XRDC_MDA_W7_9_DFMT1_DIDB_WIDTH (1U) 2849 #define RTU_XRDC_MDA_W7_9_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_DIDB_MASK) 2850 2851 #define RTU_XRDC_MDA_W7_9_DFMT1_LPID_MASK (0xF000000U) 2852 #define RTU_XRDC_MDA_W7_9_DFMT1_LPID_SHIFT (24U) 2853 #define RTU_XRDC_MDA_W7_9_DFMT1_LPID_WIDTH (4U) 2854 #define RTU_XRDC_MDA_W7_9_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_LPID_MASK) 2855 2856 #define RTU_XRDC_MDA_W7_9_DFMT1_LPE_MASK (0x10000000U) 2857 #define RTU_XRDC_MDA_W7_9_DFMT1_LPE_SHIFT (28U) 2858 #define RTU_XRDC_MDA_W7_9_DFMT1_LPE_WIDTH (1U) 2859 #define RTU_XRDC_MDA_W7_9_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_LPE_MASK) 2860 2861 #define RTU_XRDC_MDA_W7_9_DFMT1_DFMT_MASK (0x20000000U) 2862 #define RTU_XRDC_MDA_W7_9_DFMT1_DFMT_SHIFT (29U) 2863 #define RTU_XRDC_MDA_W7_9_DFMT1_DFMT_WIDTH (1U) 2864 #define RTU_XRDC_MDA_W7_9_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_DFMT_MASK) 2865 2866 #define RTU_XRDC_MDA_W7_9_DFMT1_LK1_MASK (0x40000000U) 2867 #define RTU_XRDC_MDA_W7_9_DFMT1_LK1_SHIFT (30U) 2868 #define RTU_XRDC_MDA_W7_9_DFMT1_LK1_WIDTH (1U) 2869 #define RTU_XRDC_MDA_W7_9_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_LK1_MASK) 2870 2871 #define RTU_XRDC_MDA_W7_9_DFMT1_VLD_MASK (0x80000000U) 2872 #define RTU_XRDC_MDA_W7_9_DFMT1_VLD_SHIFT (31U) 2873 #define RTU_XRDC_MDA_W7_9_DFMT1_VLD_WIDTH (1U) 2874 #define RTU_XRDC_MDA_W7_9_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_9_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_9_DFMT1_VLD_MASK) 2875 /*! @} */ 2876 2877 /*! @name MDA_W0_10_DFMT1 - Master Domain Assignment */ 2878 /*! @{ */ 2879 2880 #define RTU_XRDC_MDA_W0_10_DFMT1_DID_MASK (0xFU) 2881 #define RTU_XRDC_MDA_W0_10_DFMT1_DID_SHIFT (0U) 2882 #define RTU_XRDC_MDA_W0_10_DFMT1_DID_WIDTH (4U) 2883 #define RTU_XRDC_MDA_W0_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_DID_MASK) 2884 2885 #define RTU_XRDC_MDA_W0_10_DFMT1_PA_MASK (0x30U) 2886 #define RTU_XRDC_MDA_W0_10_DFMT1_PA_SHIFT (4U) 2887 #define RTU_XRDC_MDA_W0_10_DFMT1_PA_WIDTH (2U) 2888 #define RTU_XRDC_MDA_W0_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_PA_MASK) 2889 2890 #define RTU_XRDC_MDA_W0_10_DFMT1_SA_MASK (0xC0U) 2891 #define RTU_XRDC_MDA_W0_10_DFMT1_SA_SHIFT (6U) 2892 #define RTU_XRDC_MDA_W0_10_DFMT1_SA_WIDTH (2U) 2893 #define RTU_XRDC_MDA_W0_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_SA_MASK) 2894 2895 #define RTU_XRDC_MDA_W0_10_DFMT1_DIDB_MASK (0x100U) 2896 #define RTU_XRDC_MDA_W0_10_DFMT1_DIDB_SHIFT (8U) 2897 #define RTU_XRDC_MDA_W0_10_DFMT1_DIDB_WIDTH (1U) 2898 #define RTU_XRDC_MDA_W0_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_DIDB_MASK) 2899 2900 #define RTU_XRDC_MDA_W0_10_DFMT1_LPID_MASK (0xF000000U) 2901 #define RTU_XRDC_MDA_W0_10_DFMT1_LPID_SHIFT (24U) 2902 #define RTU_XRDC_MDA_W0_10_DFMT1_LPID_WIDTH (4U) 2903 #define RTU_XRDC_MDA_W0_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_LPID_MASK) 2904 2905 #define RTU_XRDC_MDA_W0_10_DFMT1_LPE_MASK (0x10000000U) 2906 #define RTU_XRDC_MDA_W0_10_DFMT1_LPE_SHIFT (28U) 2907 #define RTU_XRDC_MDA_W0_10_DFMT1_LPE_WIDTH (1U) 2908 #define RTU_XRDC_MDA_W0_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_LPE_MASK) 2909 2910 #define RTU_XRDC_MDA_W0_10_DFMT1_DFMT_MASK (0x20000000U) 2911 #define RTU_XRDC_MDA_W0_10_DFMT1_DFMT_SHIFT (29U) 2912 #define RTU_XRDC_MDA_W0_10_DFMT1_DFMT_WIDTH (1U) 2913 #define RTU_XRDC_MDA_W0_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_DFMT_MASK) 2914 2915 #define RTU_XRDC_MDA_W0_10_DFMT1_LK1_MASK (0x40000000U) 2916 #define RTU_XRDC_MDA_W0_10_DFMT1_LK1_SHIFT (30U) 2917 #define RTU_XRDC_MDA_W0_10_DFMT1_LK1_WIDTH (1U) 2918 #define RTU_XRDC_MDA_W0_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_LK1_MASK) 2919 2920 #define RTU_XRDC_MDA_W0_10_DFMT1_VLD_MASK (0x80000000U) 2921 #define RTU_XRDC_MDA_W0_10_DFMT1_VLD_SHIFT (31U) 2922 #define RTU_XRDC_MDA_W0_10_DFMT1_VLD_WIDTH (1U) 2923 #define RTU_XRDC_MDA_W0_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_10_DFMT1_VLD_MASK) 2924 /*! @} */ 2925 2926 /*! @name MDA_W1_10_DFMT1 - Master Domain Assignment */ 2927 /*! @{ */ 2928 2929 #define RTU_XRDC_MDA_W1_10_DFMT1_DID_MASK (0xFU) 2930 #define RTU_XRDC_MDA_W1_10_DFMT1_DID_SHIFT (0U) 2931 #define RTU_XRDC_MDA_W1_10_DFMT1_DID_WIDTH (4U) 2932 #define RTU_XRDC_MDA_W1_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_DID_MASK) 2933 2934 #define RTU_XRDC_MDA_W1_10_DFMT1_PA_MASK (0x30U) 2935 #define RTU_XRDC_MDA_W1_10_DFMT1_PA_SHIFT (4U) 2936 #define RTU_XRDC_MDA_W1_10_DFMT1_PA_WIDTH (2U) 2937 #define RTU_XRDC_MDA_W1_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_PA_MASK) 2938 2939 #define RTU_XRDC_MDA_W1_10_DFMT1_SA_MASK (0xC0U) 2940 #define RTU_XRDC_MDA_W1_10_DFMT1_SA_SHIFT (6U) 2941 #define RTU_XRDC_MDA_W1_10_DFMT1_SA_WIDTH (2U) 2942 #define RTU_XRDC_MDA_W1_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_SA_MASK) 2943 2944 #define RTU_XRDC_MDA_W1_10_DFMT1_DIDB_MASK (0x100U) 2945 #define RTU_XRDC_MDA_W1_10_DFMT1_DIDB_SHIFT (8U) 2946 #define RTU_XRDC_MDA_W1_10_DFMT1_DIDB_WIDTH (1U) 2947 #define RTU_XRDC_MDA_W1_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_DIDB_MASK) 2948 2949 #define RTU_XRDC_MDA_W1_10_DFMT1_LPID_MASK (0xF000000U) 2950 #define RTU_XRDC_MDA_W1_10_DFMT1_LPID_SHIFT (24U) 2951 #define RTU_XRDC_MDA_W1_10_DFMT1_LPID_WIDTH (4U) 2952 #define RTU_XRDC_MDA_W1_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_LPID_MASK) 2953 2954 #define RTU_XRDC_MDA_W1_10_DFMT1_LPE_MASK (0x10000000U) 2955 #define RTU_XRDC_MDA_W1_10_DFMT1_LPE_SHIFT (28U) 2956 #define RTU_XRDC_MDA_W1_10_DFMT1_LPE_WIDTH (1U) 2957 #define RTU_XRDC_MDA_W1_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_LPE_MASK) 2958 2959 #define RTU_XRDC_MDA_W1_10_DFMT1_DFMT_MASK (0x20000000U) 2960 #define RTU_XRDC_MDA_W1_10_DFMT1_DFMT_SHIFT (29U) 2961 #define RTU_XRDC_MDA_W1_10_DFMT1_DFMT_WIDTH (1U) 2962 #define RTU_XRDC_MDA_W1_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_DFMT_MASK) 2963 2964 #define RTU_XRDC_MDA_W1_10_DFMT1_LK1_MASK (0x40000000U) 2965 #define RTU_XRDC_MDA_W1_10_DFMT1_LK1_SHIFT (30U) 2966 #define RTU_XRDC_MDA_W1_10_DFMT1_LK1_WIDTH (1U) 2967 #define RTU_XRDC_MDA_W1_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_LK1_MASK) 2968 2969 #define RTU_XRDC_MDA_W1_10_DFMT1_VLD_MASK (0x80000000U) 2970 #define RTU_XRDC_MDA_W1_10_DFMT1_VLD_SHIFT (31U) 2971 #define RTU_XRDC_MDA_W1_10_DFMT1_VLD_WIDTH (1U) 2972 #define RTU_XRDC_MDA_W1_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_10_DFMT1_VLD_MASK) 2973 /*! @} */ 2974 2975 /*! @name MDA_W2_10_DFMT1 - Master Domain Assignment */ 2976 /*! @{ */ 2977 2978 #define RTU_XRDC_MDA_W2_10_DFMT1_DID_MASK (0xFU) 2979 #define RTU_XRDC_MDA_W2_10_DFMT1_DID_SHIFT (0U) 2980 #define RTU_XRDC_MDA_W2_10_DFMT1_DID_WIDTH (4U) 2981 #define RTU_XRDC_MDA_W2_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_DID_MASK) 2982 2983 #define RTU_XRDC_MDA_W2_10_DFMT1_PA_MASK (0x30U) 2984 #define RTU_XRDC_MDA_W2_10_DFMT1_PA_SHIFT (4U) 2985 #define RTU_XRDC_MDA_W2_10_DFMT1_PA_WIDTH (2U) 2986 #define RTU_XRDC_MDA_W2_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_PA_MASK) 2987 2988 #define RTU_XRDC_MDA_W2_10_DFMT1_SA_MASK (0xC0U) 2989 #define RTU_XRDC_MDA_W2_10_DFMT1_SA_SHIFT (6U) 2990 #define RTU_XRDC_MDA_W2_10_DFMT1_SA_WIDTH (2U) 2991 #define RTU_XRDC_MDA_W2_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_SA_MASK) 2992 2993 #define RTU_XRDC_MDA_W2_10_DFMT1_DIDB_MASK (0x100U) 2994 #define RTU_XRDC_MDA_W2_10_DFMT1_DIDB_SHIFT (8U) 2995 #define RTU_XRDC_MDA_W2_10_DFMT1_DIDB_WIDTH (1U) 2996 #define RTU_XRDC_MDA_W2_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_DIDB_MASK) 2997 2998 #define RTU_XRDC_MDA_W2_10_DFMT1_LPID_MASK (0xF000000U) 2999 #define RTU_XRDC_MDA_W2_10_DFMT1_LPID_SHIFT (24U) 3000 #define RTU_XRDC_MDA_W2_10_DFMT1_LPID_WIDTH (4U) 3001 #define RTU_XRDC_MDA_W2_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_LPID_MASK) 3002 3003 #define RTU_XRDC_MDA_W2_10_DFMT1_LPE_MASK (0x10000000U) 3004 #define RTU_XRDC_MDA_W2_10_DFMT1_LPE_SHIFT (28U) 3005 #define RTU_XRDC_MDA_W2_10_DFMT1_LPE_WIDTH (1U) 3006 #define RTU_XRDC_MDA_W2_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_LPE_MASK) 3007 3008 #define RTU_XRDC_MDA_W2_10_DFMT1_DFMT_MASK (0x20000000U) 3009 #define RTU_XRDC_MDA_W2_10_DFMT1_DFMT_SHIFT (29U) 3010 #define RTU_XRDC_MDA_W2_10_DFMT1_DFMT_WIDTH (1U) 3011 #define RTU_XRDC_MDA_W2_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_DFMT_MASK) 3012 3013 #define RTU_XRDC_MDA_W2_10_DFMT1_LK1_MASK (0x40000000U) 3014 #define RTU_XRDC_MDA_W2_10_DFMT1_LK1_SHIFT (30U) 3015 #define RTU_XRDC_MDA_W2_10_DFMT1_LK1_WIDTH (1U) 3016 #define RTU_XRDC_MDA_W2_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_LK1_MASK) 3017 3018 #define RTU_XRDC_MDA_W2_10_DFMT1_VLD_MASK (0x80000000U) 3019 #define RTU_XRDC_MDA_W2_10_DFMT1_VLD_SHIFT (31U) 3020 #define RTU_XRDC_MDA_W2_10_DFMT1_VLD_WIDTH (1U) 3021 #define RTU_XRDC_MDA_W2_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_10_DFMT1_VLD_MASK) 3022 /*! @} */ 3023 3024 /*! @name MDA_W3_10_DFMT1 - Master Domain Assignment */ 3025 /*! @{ */ 3026 3027 #define RTU_XRDC_MDA_W3_10_DFMT1_DID_MASK (0xFU) 3028 #define RTU_XRDC_MDA_W3_10_DFMT1_DID_SHIFT (0U) 3029 #define RTU_XRDC_MDA_W3_10_DFMT1_DID_WIDTH (4U) 3030 #define RTU_XRDC_MDA_W3_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_DID_MASK) 3031 3032 #define RTU_XRDC_MDA_W3_10_DFMT1_PA_MASK (0x30U) 3033 #define RTU_XRDC_MDA_W3_10_DFMT1_PA_SHIFT (4U) 3034 #define RTU_XRDC_MDA_W3_10_DFMT1_PA_WIDTH (2U) 3035 #define RTU_XRDC_MDA_W3_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_PA_MASK) 3036 3037 #define RTU_XRDC_MDA_W3_10_DFMT1_SA_MASK (0xC0U) 3038 #define RTU_XRDC_MDA_W3_10_DFMT1_SA_SHIFT (6U) 3039 #define RTU_XRDC_MDA_W3_10_DFMT1_SA_WIDTH (2U) 3040 #define RTU_XRDC_MDA_W3_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_SA_MASK) 3041 3042 #define RTU_XRDC_MDA_W3_10_DFMT1_DIDB_MASK (0x100U) 3043 #define RTU_XRDC_MDA_W3_10_DFMT1_DIDB_SHIFT (8U) 3044 #define RTU_XRDC_MDA_W3_10_DFMT1_DIDB_WIDTH (1U) 3045 #define RTU_XRDC_MDA_W3_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_DIDB_MASK) 3046 3047 #define RTU_XRDC_MDA_W3_10_DFMT1_LPID_MASK (0xF000000U) 3048 #define RTU_XRDC_MDA_W3_10_DFMT1_LPID_SHIFT (24U) 3049 #define RTU_XRDC_MDA_W3_10_DFMT1_LPID_WIDTH (4U) 3050 #define RTU_XRDC_MDA_W3_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_LPID_MASK) 3051 3052 #define RTU_XRDC_MDA_W3_10_DFMT1_LPE_MASK (0x10000000U) 3053 #define RTU_XRDC_MDA_W3_10_DFMT1_LPE_SHIFT (28U) 3054 #define RTU_XRDC_MDA_W3_10_DFMT1_LPE_WIDTH (1U) 3055 #define RTU_XRDC_MDA_W3_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_LPE_MASK) 3056 3057 #define RTU_XRDC_MDA_W3_10_DFMT1_DFMT_MASK (0x20000000U) 3058 #define RTU_XRDC_MDA_W3_10_DFMT1_DFMT_SHIFT (29U) 3059 #define RTU_XRDC_MDA_W3_10_DFMT1_DFMT_WIDTH (1U) 3060 #define RTU_XRDC_MDA_W3_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_DFMT_MASK) 3061 3062 #define RTU_XRDC_MDA_W3_10_DFMT1_LK1_MASK (0x40000000U) 3063 #define RTU_XRDC_MDA_W3_10_DFMT1_LK1_SHIFT (30U) 3064 #define RTU_XRDC_MDA_W3_10_DFMT1_LK1_WIDTH (1U) 3065 #define RTU_XRDC_MDA_W3_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_LK1_MASK) 3066 3067 #define RTU_XRDC_MDA_W3_10_DFMT1_VLD_MASK (0x80000000U) 3068 #define RTU_XRDC_MDA_W3_10_DFMT1_VLD_SHIFT (31U) 3069 #define RTU_XRDC_MDA_W3_10_DFMT1_VLD_WIDTH (1U) 3070 #define RTU_XRDC_MDA_W3_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_10_DFMT1_VLD_MASK) 3071 /*! @} */ 3072 3073 /*! @name MDA_W4_10_DFMT1 - Master Domain Assignment */ 3074 /*! @{ */ 3075 3076 #define RTU_XRDC_MDA_W4_10_DFMT1_DID_MASK (0xFU) 3077 #define RTU_XRDC_MDA_W4_10_DFMT1_DID_SHIFT (0U) 3078 #define RTU_XRDC_MDA_W4_10_DFMT1_DID_WIDTH (4U) 3079 #define RTU_XRDC_MDA_W4_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_DID_MASK) 3080 3081 #define RTU_XRDC_MDA_W4_10_DFMT1_PA_MASK (0x30U) 3082 #define RTU_XRDC_MDA_W4_10_DFMT1_PA_SHIFT (4U) 3083 #define RTU_XRDC_MDA_W4_10_DFMT1_PA_WIDTH (2U) 3084 #define RTU_XRDC_MDA_W4_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_PA_MASK) 3085 3086 #define RTU_XRDC_MDA_W4_10_DFMT1_SA_MASK (0xC0U) 3087 #define RTU_XRDC_MDA_W4_10_DFMT1_SA_SHIFT (6U) 3088 #define RTU_XRDC_MDA_W4_10_DFMT1_SA_WIDTH (2U) 3089 #define RTU_XRDC_MDA_W4_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_SA_MASK) 3090 3091 #define RTU_XRDC_MDA_W4_10_DFMT1_DIDB_MASK (0x100U) 3092 #define RTU_XRDC_MDA_W4_10_DFMT1_DIDB_SHIFT (8U) 3093 #define RTU_XRDC_MDA_W4_10_DFMT1_DIDB_WIDTH (1U) 3094 #define RTU_XRDC_MDA_W4_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_DIDB_MASK) 3095 3096 #define RTU_XRDC_MDA_W4_10_DFMT1_LPID_MASK (0xF000000U) 3097 #define RTU_XRDC_MDA_W4_10_DFMT1_LPID_SHIFT (24U) 3098 #define RTU_XRDC_MDA_W4_10_DFMT1_LPID_WIDTH (4U) 3099 #define RTU_XRDC_MDA_W4_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_LPID_MASK) 3100 3101 #define RTU_XRDC_MDA_W4_10_DFMT1_LPE_MASK (0x10000000U) 3102 #define RTU_XRDC_MDA_W4_10_DFMT1_LPE_SHIFT (28U) 3103 #define RTU_XRDC_MDA_W4_10_DFMT1_LPE_WIDTH (1U) 3104 #define RTU_XRDC_MDA_W4_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_LPE_MASK) 3105 3106 #define RTU_XRDC_MDA_W4_10_DFMT1_DFMT_MASK (0x20000000U) 3107 #define RTU_XRDC_MDA_W4_10_DFMT1_DFMT_SHIFT (29U) 3108 #define RTU_XRDC_MDA_W4_10_DFMT1_DFMT_WIDTH (1U) 3109 #define RTU_XRDC_MDA_W4_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_DFMT_MASK) 3110 3111 #define RTU_XRDC_MDA_W4_10_DFMT1_LK1_MASK (0x40000000U) 3112 #define RTU_XRDC_MDA_W4_10_DFMT1_LK1_SHIFT (30U) 3113 #define RTU_XRDC_MDA_W4_10_DFMT1_LK1_WIDTH (1U) 3114 #define RTU_XRDC_MDA_W4_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_LK1_MASK) 3115 3116 #define RTU_XRDC_MDA_W4_10_DFMT1_VLD_MASK (0x80000000U) 3117 #define RTU_XRDC_MDA_W4_10_DFMT1_VLD_SHIFT (31U) 3118 #define RTU_XRDC_MDA_W4_10_DFMT1_VLD_WIDTH (1U) 3119 #define RTU_XRDC_MDA_W4_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_10_DFMT1_VLD_MASK) 3120 /*! @} */ 3121 3122 /*! @name MDA_W5_10_DFMT1 - Master Domain Assignment */ 3123 /*! @{ */ 3124 3125 #define RTU_XRDC_MDA_W5_10_DFMT1_DID_MASK (0xFU) 3126 #define RTU_XRDC_MDA_W5_10_DFMT1_DID_SHIFT (0U) 3127 #define RTU_XRDC_MDA_W5_10_DFMT1_DID_WIDTH (4U) 3128 #define RTU_XRDC_MDA_W5_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_DID_MASK) 3129 3130 #define RTU_XRDC_MDA_W5_10_DFMT1_PA_MASK (0x30U) 3131 #define RTU_XRDC_MDA_W5_10_DFMT1_PA_SHIFT (4U) 3132 #define RTU_XRDC_MDA_W5_10_DFMT1_PA_WIDTH (2U) 3133 #define RTU_XRDC_MDA_W5_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_PA_MASK) 3134 3135 #define RTU_XRDC_MDA_W5_10_DFMT1_SA_MASK (0xC0U) 3136 #define RTU_XRDC_MDA_W5_10_DFMT1_SA_SHIFT (6U) 3137 #define RTU_XRDC_MDA_W5_10_DFMT1_SA_WIDTH (2U) 3138 #define RTU_XRDC_MDA_W5_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_SA_MASK) 3139 3140 #define RTU_XRDC_MDA_W5_10_DFMT1_DIDB_MASK (0x100U) 3141 #define RTU_XRDC_MDA_W5_10_DFMT1_DIDB_SHIFT (8U) 3142 #define RTU_XRDC_MDA_W5_10_DFMT1_DIDB_WIDTH (1U) 3143 #define RTU_XRDC_MDA_W5_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_DIDB_MASK) 3144 3145 #define RTU_XRDC_MDA_W5_10_DFMT1_LPID_MASK (0xF000000U) 3146 #define RTU_XRDC_MDA_W5_10_DFMT1_LPID_SHIFT (24U) 3147 #define RTU_XRDC_MDA_W5_10_DFMT1_LPID_WIDTH (4U) 3148 #define RTU_XRDC_MDA_W5_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_LPID_MASK) 3149 3150 #define RTU_XRDC_MDA_W5_10_DFMT1_LPE_MASK (0x10000000U) 3151 #define RTU_XRDC_MDA_W5_10_DFMT1_LPE_SHIFT (28U) 3152 #define RTU_XRDC_MDA_W5_10_DFMT1_LPE_WIDTH (1U) 3153 #define RTU_XRDC_MDA_W5_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_LPE_MASK) 3154 3155 #define RTU_XRDC_MDA_W5_10_DFMT1_DFMT_MASK (0x20000000U) 3156 #define RTU_XRDC_MDA_W5_10_DFMT1_DFMT_SHIFT (29U) 3157 #define RTU_XRDC_MDA_W5_10_DFMT1_DFMT_WIDTH (1U) 3158 #define RTU_XRDC_MDA_W5_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_DFMT_MASK) 3159 3160 #define RTU_XRDC_MDA_W5_10_DFMT1_LK1_MASK (0x40000000U) 3161 #define RTU_XRDC_MDA_W5_10_DFMT1_LK1_SHIFT (30U) 3162 #define RTU_XRDC_MDA_W5_10_DFMT1_LK1_WIDTH (1U) 3163 #define RTU_XRDC_MDA_W5_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_LK1_MASK) 3164 3165 #define RTU_XRDC_MDA_W5_10_DFMT1_VLD_MASK (0x80000000U) 3166 #define RTU_XRDC_MDA_W5_10_DFMT1_VLD_SHIFT (31U) 3167 #define RTU_XRDC_MDA_W5_10_DFMT1_VLD_WIDTH (1U) 3168 #define RTU_XRDC_MDA_W5_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_10_DFMT1_VLD_MASK) 3169 /*! @} */ 3170 3171 /*! @name MDA_W6_10_DFMT1 - Master Domain Assignment */ 3172 /*! @{ */ 3173 3174 #define RTU_XRDC_MDA_W6_10_DFMT1_DID_MASK (0xFU) 3175 #define RTU_XRDC_MDA_W6_10_DFMT1_DID_SHIFT (0U) 3176 #define RTU_XRDC_MDA_W6_10_DFMT1_DID_WIDTH (4U) 3177 #define RTU_XRDC_MDA_W6_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_DID_MASK) 3178 3179 #define RTU_XRDC_MDA_W6_10_DFMT1_PA_MASK (0x30U) 3180 #define RTU_XRDC_MDA_W6_10_DFMT1_PA_SHIFT (4U) 3181 #define RTU_XRDC_MDA_W6_10_DFMT1_PA_WIDTH (2U) 3182 #define RTU_XRDC_MDA_W6_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_PA_MASK) 3183 3184 #define RTU_XRDC_MDA_W6_10_DFMT1_SA_MASK (0xC0U) 3185 #define RTU_XRDC_MDA_W6_10_DFMT1_SA_SHIFT (6U) 3186 #define RTU_XRDC_MDA_W6_10_DFMT1_SA_WIDTH (2U) 3187 #define RTU_XRDC_MDA_W6_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_SA_MASK) 3188 3189 #define RTU_XRDC_MDA_W6_10_DFMT1_DIDB_MASK (0x100U) 3190 #define RTU_XRDC_MDA_W6_10_DFMT1_DIDB_SHIFT (8U) 3191 #define RTU_XRDC_MDA_W6_10_DFMT1_DIDB_WIDTH (1U) 3192 #define RTU_XRDC_MDA_W6_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_DIDB_MASK) 3193 3194 #define RTU_XRDC_MDA_W6_10_DFMT1_LPID_MASK (0xF000000U) 3195 #define RTU_XRDC_MDA_W6_10_DFMT1_LPID_SHIFT (24U) 3196 #define RTU_XRDC_MDA_W6_10_DFMT1_LPID_WIDTH (4U) 3197 #define RTU_XRDC_MDA_W6_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_LPID_MASK) 3198 3199 #define RTU_XRDC_MDA_W6_10_DFMT1_LPE_MASK (0x10000000U) 3200 #define RTU_XRDC_MDA_W6_10_DFMT1_LPE_SHIFT (28U) 3201 #define RTU_XRDC_MDA_W6_10_DFMT1_LPE_WIDTH (1U) 3202 #define RTU_XRDC_MDA_W6_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_LPE_MASK) 3203 3204 #define RTU_XRDC_MDA_W6_10_DFMT1_DFMT_MASK (0x20000000U) 3205 #define RTU_XRDC_MDA_W6_10_DFMT1_DFMT_SHIFT (29U) 3206 #define RTU_XRDC_MDA_W6_10_DFMT1_DFMT_WIDTH (1U) 3207 #define RTU_XRDC_MDA_W6_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_DFMT_MASK) 3208 3209 #define RTU_XRDC_MDA_W6_10_DFMT1_LK1_MASK (0x40000000U) 3210 #define RTU_XRDC_MDA_W6_10_DFMT1_LK1_SHIFT (30U) 3211 #define RTU_XRDC_MDA_W6_10_DFMT1_LK1_WIDTH (1U) 3212 #define RTU_XRDC_MDA_W6_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_LK1_MASK) 3213 3214 #define RTU_XRDC_MDA_W6_10_DFMT1_VLD_MASK (0x80000000U) 3215 #define RTU_XRDC_MDA_W6_10_DFMT1_VLD_SHIFT (31U) 3216 #define RTU_XRDC_MDA_W6_10_DFMT1_VLD_WIDTH (1U) 3217 #define RTU_XRDC_MDA_W6_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_10_DFMT1_VLD_MASK) 3218 /*! @} */ 3219 3220 /*! @name MDA_W7_10_DFMT1 - Master Domain Assignment */ 3221 /*! @{ */ 3222 3223 #define RTU_XRDC_MDA_W7_10_DFMT1_DID_MASK (0xFU) 3224 #define RTU_XRDC_MDA_W7_10_DFMT1_DID_SHIFT (0U) 3225 #define RTU_XRDC_MDA_W7_10_DFMT1_DID_WIDTH (4U) 3226 #define RTU_XRDC_MDA_W7_10_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_DID_MASK) 3227 3228 #define RTU_XRDC_MDA_W7_10_DFMT1_PA_MASK (0x30U) 3229 #define RTU_XRDC_MDA_W7_10_DFMT1_PA_SHIFT (4U) 3230 #define RTU_XRDC_MDA_W7_10_DFMT1_PA_WIDTH (2U) 3231 #define RTU_XRDC_MDA_W7_10_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_PA_MASK) 3232 3233 #define RTU_XRDC_MDA_W7_10_DFMT1_SA_MASK (0xC0U) 3234 #define RTU_XRDC_MDA_W7_10_DFMT1_SA_SHIFT (6U) 3235 #define RTU_XRDC_MDA_W7_10_DFMT1_SA_WIDTH (2U) 3236 #define RTU_XRDC_MDA_W7_10_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_SA_MASK) 3237 3238 #define RTU_XRDC_MDA_W7_10_DFMT1_DIDB_MASK (0x100U) 3239 #define RTU_XRDC_MDA_W7_10_DFMT1_DIDB_SHIFT (8U) 3240 #define RTU_XRDC_MDA_W7_10_DFMT1_DIDB_WIDTH (1U) 3241 #define RTU_XRDC_MDA_W7_10_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_DIDB_MASK) 3242 3243 #define RTU_XRDC_MDA_W7_10_DFMT1_LPID_MASK (0xF000000U) 3244 #define RTU_XRDC_MDA_W7_10_DFMT1_LPID_SHIFT (24U) 3245 #define RTU_XRDC_MDA_W7_10_DFMT1_LPID_WIDTH (4U) 3246 #define RTU_XRDC_MDA_W7_10_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_LPID_MASK) 3247 3248 #define RTU_XRDC_MDA_W7_10_DFMT1_LPE_MASK (0x10000000U) 3249 #define RTU_XRDC_MDA_W7_10_DFMT1_LPE_SHIFT (28U) 3250 #define RTU_XRDC_MDA_W7_10_DFMT1_LPE_WIDTH (1U) 3251 #define RTU_XRDC_MDA_W7_10_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_LPE_MASK) 3252 3253 #define RTU_XRDC_MDA_W7_10_DFMT1_DFMT_MASK (0x20000000U) 3254 #define RTU_XRDC_MDA_W7_10_DFMT1_DFMT_SHIFT (29U) 3255 #define RTU_XRDC_MDA_W7_10_DFMT1_DFMT_WIDTH (1U) 3256 #define RTU_XRDC_MDA_W7_10_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_DFMT_MASK) 3257 3258 #define RTU_XRDC_MDA_W7_10_DFMT1_LK1_MASK (0x40000000U) 3259 #define RTU_XRDC_MDA_W7_10_DFMT1_LK1_SHIFT (30U) 3260 #define RTU_XRDC_MDA_W7_10_DFMT1_LK1_WIDTH (1U) 3261 #define RTU_XRDC_MDA_W7_10_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_LK1_MASK) 3262 3263 #define RTU_XRDC_MDA_W7_10_DFMT1_VLD_MASK (0x80000000U) 3264 #define RTU_XRDC_MDA_W7_10_DFMT1_VLD_SHIFT (31U) 3265 #define RTU_XRDC_MDA_W7_10_DFMT1_VLD_WIDTH (1U) 3266 #define RTU_XRDC_MDA_W7_10_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_10_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_10_DFMT1_VLD_MASK) 3267 /*! @} */ 3268 3269 /*! @name MDA_W0_11_DFMT1 - Master Domain Assignment */ 3270 /*! @{ */ 3271 3272 #define RTU_XRDC_MDA_W0_11_DFMT1_DID_MASK (0xFU) 3273 #define RTU_XRDC_MDA_W0_11_DFMT1_DID_SHIFT (0U) 3274 #define RTU_XRDC_MDA_W0_11_DFMT1_DID_WIDTH (4U) 3275 #define RTU_XRDC_MDA_W0_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_DID_MASK) 3276 3277 #define RTU_XRDC_MDA_W0_11_DFMT1_PA_MASK (0x30U) 3278 #define RTU_XRDC_MDA_W0_11_DFMT1_PA_SHIFT (4U) 3279 #define RTU_XRDC_MDA_W0_11_DFMT1_PA_WIDTH (2U) 3280 #define RTU_XRDC_MDA_W0_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_PA_MASK) 3281 3282 #define RTU_XRDC_MDA_W0_11_DFMT1_SA_MASK (0xC0U) 3283 #define RTU_XRDC_MDA_W0_11_DFMT1_SA_SHIFT (6U) 3284 #define RTU_XRDC_MDA_W0_11_DFMT1_SA_WIDTH (2U) 3285 #define RTU_XRDC_MDA_W0_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_SA_MASK) 3286 3287 #define RTU_XRDC_MDA_W0_11_DFMT1_DIDB_MASK (0x100U) 3288 #define RTU_XRDC_MDA_W0_11_DFMT1_DIDB_SHIFT (8U) 3289 #define RTU_XRDC_MDA_W0_11_DFMT1_DIDB_WIDTH (1U) 3290 #define RTU_XRDC_MDA_W0_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_DIDB_MASK) 3291 3292 #define RTU_XRDC_MDA_W0_11_DFMT1_LPID_MASK (0xF000000U) 3293 #define RTU_XRDC_MDA_W0_11_DFMT1_LPID_SHIFT (24U) 3294 #define RTU_XRDC_MDA_W0_11_DFMT1_LPID_WIDTH (4U) 3295 #define RTU_XRDC_MDA_W0_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_LPID_MASK) 3296 3297 #define RTU_XRDC_MDA_W0_11_DFMT1_LPE_MASK (0x10000000U) 3298 #define RTU_XRDC_MDA_W0_11_DFMT1_LPE_SHIFT (28U) 3299 #define RTU_XRDC_MDA_W0_11_DFMT1_LPE_WIDTH (1U) 3300 #define RTU_XRDC_MDA_W0_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_LPE_MASK) 3301 3302 #define RTU_XRDC_MDA_W0_11_DFMT1_DFMT_MASK (0x20000000U) 3303 #define RTU_XRDC_MDA_W0_11_DFMT1_DFMT_SHIFT (29U) 3304 #define RTU_XRDC_MDA_W0_11_DFMT1_DFMT_WIDTH (1U) 3305 #define RTU_XRDC_MDA_W0_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_DFMT_MASK) 3306 3307 #define RTU_XRDC_MDA_W0_11_DFMT1_LK1_MASK (0x40000000U) 3308 #define RTU_XRDC_MDA_W0_11_DFMT1_LK1_SHIFT (30U) 3309 #define RTU_XRDC_MDA_W0_11_DFMT1_LK1_WIDTH (1U) 3310 #define RTU_XRDC_MDA_W0_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_LK1_MASK) 3311 3312 #define RTU_XRDC_MDA_W0_11_DFMT1_VLD_MASK (0x80000000U) 3313 #define RTU_XRDC_MDA_W0_11_DFMT1_VLD_SHIFT (31U) 3314 #define RTU_XRDC_MDA_W0_11_DFMT1_VLD_WIDTH (1U) 3315 #define RTU_XRDC_MDA_W0_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_11_DFMT1_VLD_MASK) 3316 /*! @} */ 3317 3318 /*! @name MDA_W1_11_DFMT1 - Master Domain Assignment */ 3319 /*! @{ */ 3320 3321 #define RTU_XRDC_MDA_W1_11_DFMT1_DID_MASK (0xFU) 3322 #define RTU_XRDC_MDA_W1_11_DFMT1_DID_SHIFT (0U) 3323 #define RTU_XRDC_MDA_W1_11_DFMT1_DID_WIDTH (4U) 3324 #define RTU_XRDC_MDA_W1_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_DID_MASK) 3325 3326 #define RTU_XRDC_MDA_W1_11_DFMT1_PA_MASK (0x30U) 3327 #define RTU_XRDC_MDA_W1_11_DFMT1_PA_SHIFT (4U) 3328 #define RTU_XRDC_MDA_W1_11_DFMT1_PA_WIDTH (2U) 3329 #define RTU_XRDC_MDA_W1_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_PA_MASK) 3330 3331 #define RTU_XRDC_MDA_W1_11_DFMT1_SA_MASK (0xC0U) 3332 #define RTU_XRDC_MDA_W1_11_DFMT1_SA_SHIFT (6U) 3333 #define RTU_XRDC_MDA_W1_11_DFMT1_SA_WIDTH (2U) 3334 #define RTU_XRDC_MDA_W1_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_SA_MASK) 3335 3336 #define RTU_XRDC_MDA_W1_11_DFMT1_DIDB_MASK (0x100U) 3337 #define RTU_XRDC_MDA_W1_11_DFMT1_DIDB_SHIFT (8U) 3338 #define RTU_XRDC_MDA_W1_11_DFMT1_DIDB_WIDTH (1U) 3339 #define RTU_XRDC_MDA_W1_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_DIDB_MASK) 3340 3341 #define RTU_XRDC_MDA_W1_11_DFMT1_LPID_MASK (0xF000000U) 3342 #define RTU_XRDC_MDA_W1_11_DFMT1_LPID_SHIFT (24U) 3343 #define RTU_XRDC_MDA_W1_11_DFMT1_LPID_WIDTH (4U) 3344 #define RTU_XRDC_MDA_W1_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_LPID_MASK) 3345 3346 #define RTU_XRDC_MDA_W1_11_DFMT1_LPE_MASK (0x10000000U) 3347 #define RTU_XRDC_MDA_W1_11_DFMT1_LPE_SHIFT (28U) 3348 #define RTU_XRDC_MDA_W1_11_DFMT1_LPE_WIDTH (1U) 3349 #define RTU_XRDC_MDA_W1_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_LPE_MASK) 3350 3351 #define RTU_XRDC_MDA_W1_11_DFMT1_DFMT_MASK (0x20000000U) 3352 #define RTU_XRDC_MDA_W1_11_DFMT1_DFMT_SHIFT (29U) 3353 #define RTU_XRDC_MDA_W1_11_DFMT1_DFMT_WIDTH (1U) 3354 #define RTU_XRDC_MDA_W1_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_DFMT_MASK) 3355 3356 #define RTU_XRDC_MDA_W1_11_DFMT1_LK1_MASK (0x40000000U) 3357 #define RTU_XRDC_MDA_W1_11_DFMT1_LK1_SHIFT (30U) 3358 #define RTU_XRDC_MDA_W1_11_DFMT1_LK1_WIDTH (1U) 3359 #define RTU_XRDC_MDA_W1_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_LK1_MASK) 3360 3361 #define RTU_XRDC_MDA_W1_11_DFMT1_VLD_MASK (0x80000000U) 3362 #define RTU_XRDC_MDA_W1_11_DFMT1_VLD_SHIFT (31U) 3363 #define RTU_XRDC_MDA_W1_11_DFMT1_VLD_WIDTH (1U) 3364 #define RTU_XRDC_MDA_W1_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W1_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W1_11_DFMT1_VLD_MASK) 3365 /*! @} */ 3366 3367 /*! @name MDA_W2_11_DFMT1 - Master Domain Assignment */ 3368 /*! @{ */ 3369 3370 #define RTU_XRDC_MDA_W2_11_DFMT1_DID_MASK (0xFU) 3371 #define RTU_XRDC_MDA_W2_11_DFMT1_DID_SHIFT (0U) 3372 #define RTU_XRDC_MDA_W2_11_DFMT1_DID_WIDTH (4U) 3373 #define RTU_XRDC_MDA_W2_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_DID_MASK) 3374 3375 #define RTU_XRDC_MDA_W2_11_DFMT1_PA_MASK (0x30U) 3376 #define RTU_XRDC_MDA_W2_11_DFMT1_PA_SHIFT (4U) 3377 #define RTU_XRDC_MDA_W2_11_DFMT1_PA_WIDTH (2U) 3378 #define RTU_XRDC_MDA_W2_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_PA_MASK) 3379 3380 #define RTU_XRDC_MDA_W2_11_DFMT1_SA_MASK (0xC0U) 3381 #define RTU_XRDC_MDA_W2_11_DFMT1_SA_SHIFT (6U) 3382 #define RTU_XRDC_MDA_W2_11_DFMT1_SA_WIDTH (2U) 3383 #define RTU_XRDC_MDA_W2_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_SA_MASK) 3384 3385 #define RTU_XRDC_MDA_W2_11_DFMT1_DIDB_MASK (0x100U) 3386 #define RTU_XRDC_MDA_W2_11_DFMT1_DIDB_SHIFT (8U) 3387 #define RTU_XRDC_MDA_W2_11_DFMT1_DIDB_WIDTH (1U) 3388 #define RTU_XRDC_MDA_W2_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_DIDB_MASK) 3389 3390 #define RTU_XRDC_MDA_W2_11_DFMT1_LPID_MASK (0xF000000U) 3391 #define RTU_XRDC_MDA_W2_11_DFMT1_LPID_SHIFT (24U) 3392 #define RTU_XRDC_MDA_W2_11_DFMT1_LPID_WIDTH (4U) 3393 #define RTU_XRDC_MDA_W2_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_LPID_MASK) 3394 3395 #define RTU_XRDC_MDA_W2_11_DFMT1_LPE_MASK (0x10000000U) 3396 #define RTU_XRDC_MDA_W2_11_DFMT1_LPE_SHIFT (28U) 3397 #define RTU_XRDC_MDA_W2_11_DFMT1_LPE_WIDTH (1U) 3398 #define RTU_XRDC_MDA_W2_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_LPE_MASK) 3399 3400 #define RTU_XRDC_MDA_W2_11_DFMT1_DFMT_MASK (0x20000000U) 3401 #define RTU_XRDC_MDA_W2_11_DFMT1_DFMT_SHIFT (29U) 3402 #define RTU_XRDC_MDA_W2_11_DFMT1_DFMT_WIDTH (1U) 3403 #define RTU_XRDC_MDA_W2_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_DFMT_MASK) 3404 3405 #define RTU_XRDC_MDA_W2_11_DFMT1_LK1_MASK (0x40000000U) 3406 #define RTU_XRDC_MDA_W2_11_DFMT1_LK1_SHIFT (30U) 3407 #define RTU_XRDC_MDA_W2_11_DFMT1_LK1_WIDTH (1U) 3408 #define RTU_XRDC_MDA_W2_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_LK1_MASK) 3409 3410 #define RTU_XRDC_MDA_W2_11_DFMT1_VLD_MASK (0x80000000U) 3411 #define RTU_XRDC_MDA_W2_11_DFMT1_VLD_SHIFT (31U) 3412 #define RTU_XRDC_MDA_W2_11_DFMT1_VLD_WIDTH (1U) 3413 #define RTU_XRDC_MDA_W2_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W2_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W2_11_DFMT1_VLD_MASK) 3414 /*! @} */ 3415 3416 /*! @name MDA_W3_11_DFMT1 - Master Domain Assignment */ 3417 /*! @{ */ 3418 3419 #define RTU_XRDC_MDA_W3_11_DFMT1_DID_MASK (0xFU) 3420 #define RTU_XRDC_MDA_W3_11_DFMT1_DID_SHIFT (0U) 3421 #define RTU_XRDC_MDA_W3_11_DFMT1_DID_WIDTH (4U) 3422 #define RTU_XRDC_MDA_W3_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_DID_MASK) 3423 3424 #define RTU_XRDC_MDA_W3_11_DFMT1_PA_MASK (0x30U) 3425 #define RTU_XRDC_MDA_W3_11_DFMT1_PA_SHIFT (4U) 3426 #define RTU_XRDC_MDA_W3_11_DFMT1_PA_WIDTH (2U) 3427 #define RTU_XRDC_MDA_W3_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_PA_MASK) 3428 3429 #define RTU_XRDC_MDA_W3_11_DFMT1_SA_MASK (0xC0U) 3430 #define RTU_XRDC_MDA_W3_11_DFMT1_SA_SHIFT (6U) 3431 #define RTU_XRDC_MDA_W3_11_DFMT1_SA_WIDTH (2U) 3432 #define RTU_XRDC_MDA_W3_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_SA_MASK) 3433 3434 #define RTU_XRDC_MDA_W3_11_DFMT1_DIDB_MASK (0x100U) 3435 #define RTU_XRDC_MDA_W3_11_DFMT1_DIDB_SHIFT (8U) 3436 #define RTU_XRDC_MDA_W3_11_DFMT1_DIDB_WIDTH (1U) 3437 #define RTU_XRDC_MDA_W3_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_DIDB_MASK) 3438 3439 #define RTU_XRDC_MDA_W3_11_DFMT1_LPID_MASK (0xF000000U) 3440 #define RTU_XRDC_MDA_W3_11_DFMT1_LPID_SHIFT (24U) 3441 #define RTU_XRDC_MDA_W3_11_DFMT1_LPID_WIDTH (4U) 3442 #define RTU_XRDC_MDA_W3_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_LPID_MASK) 3443 3444 #define RTU_XRDC_MDA_W3_11_DFMT1_LPE_MASK (0x10000000U) 3445 #define RTU_XRDC_MDA_W3_11_DFMT1_LPE_SHIFT (28U) 3446 #define RTU_XRDC_MDA_W3_11_DFMT1_LPE_WIDTH (1U) 3447 #define RTU_XRDC_MDA_W3_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_LPE_MASK) 3448 3449 #define RTU_XRDC_MDA_W3_11_DFMT1_DFMT_MASK (0x20000000U) 3450 #define RTU_XRDC_MDA_W3_11_DFMT1_DFMT_SHIFT (29U) 3451 #define RTU_XRDC_MDA_W3_11_DFMT1_DFMT_WIDTH (1U) 3452 #define RTU_XRDC_MDA_W3_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_DFMT_MASK) 3453 3454 #define RTU_XRDC_MDA_W3_11_DFMT1_LK1_MASK (0x40000000U) 3455 #define RTU_XRDC_MDA_W3_11_DFMT1_LK1_SHIFT (30U) 3456 #define RTU_XRDC_MDA_W3_11_DFMT1_LK1_WIDTH (1U) 3457 #define RTU_XRDC_MDA_W3_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_LK1_MASK) 3458 3459 #define RTU_XRDC_MDA_W3_11_DFMT1_VLD_MASK (0x80000000U) 3460 #define RTU_XRDC_MDA_W3_11_DFMT1_VLD_SHIFT (31U) 3461 #define RTU_XRDC_MDA_W3_11_DFMT1_VLD_WIDTH (1U) 3462 #define RTU_XRDC_MDA_W3_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W3_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W3_11_DFMT1_VLD_MASK) 3463 /*! @} */ 3464 3465 /*! @name MDA_W4_11_DFMT1 - Master Domain Assignment */ 3466 /*! @{ */ 3467 3468 #define RTU_XRDC_MDA_W4_11_DFMT1_DID_MASK (0xFU) 3469 #define RTU_XRDC_MDA_W4_11_DFMT1_DID_SHIFT (0U) 3470 #define RTU_XRDC_MDA_W4_11_DFMT1_DID_WIDTH (4U) 3471 #define RTU_XRDC_MDA_W4_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_DID_MASK) 3472 3473 #define RTU_XRDC_MDA_W4_11_DFMT1_PA_MASK (0x30U) 3474 #define RTU_XRDC_MDA_W4_11_DFMT1_PA_SHIFT (4U) 3475 #define RTU_XRDC_MDA_W4_11_DFMT1_PA_WIDTH (2U) 3476 #define RTU_XRDC_MDA_W4_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_PA_MASK) 3477 3478 #define RTU_XRDC_MDA_W4_11_DFMT1_SA_MASK (0xC0U) 3479 #define RTU_XRDC_MDA_W4_11_DFMT1_SA_SHIFT (6U) 3480 #define RTU_XRDC_MDA_W4_11_DFMT1_SA_WIDTH (2U) 3481 #define RTU_XRDC_MDA_W4_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_SA_MASK) 3482 3483 #define RTU_XRDC_MDA_W4_11_DFMT1_DIDB_MASK (0x100U) 3484 #define RTU_XRDC_MDA_W4_11_DFMT1_DIDB_SHIFT (8U) 3485 #define RTU_XRDC_MDA_W4_11_DFMT1_DIDB_WIDTH (1U) 3486 #define RTU_XRDC_MDA_W4_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_DIDB_MASK) 3487 3488 #define RTU_XRDC_MDA_W4_11_DFMT1_LPID_MASK (0xF000000U) 3489 #define RTU_XRDC_MDA_W4_11_DFMT1_LPID_SHIFT (24U) 3490 #define RTU_XRDC_MDA_W4_11_DFMT1_LPID_WIDTH (4U) 3491 #define RTU_XRDC_MDA_W4_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_LPID_MASK) 3492 3493 #define RTU_XRDC_MDA_W4_11_DFMT1_LPE_MASK (0x10000000U) 3494 #define RTU_XRDC_MDA_W4_11_DFMT1_LPE_SHIFT (28U) 3495 #define RTU_XRDC_MDA_W4_11_DFMT1_LPE_WIDTH (1U) 3496 #define RTU_XRDC_MDA_W4_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_LPE_MASK) 3497 3498 #define RTU_XRDC_MDA_W4_11_DFMT1_DFMT_MASK (0x20000000U) 3499 #define RTU_XRDC_MDA_W4_11_DFMT1_DFMT_SHIFT (29U) 3500 #define RTU_XRDC_MDA_W4_11_DFMT1_DFMT_WIDTH (1U) 3501 #define RTU_XRDC_MDA_W4_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_DFMT_MASK) 3502 3503 #define RTU_XRDC_MDA_W4_11_DFMT1_LK1_MASK (0x40000000U) 3504 #define RTU_XRDC_MDA_W4_11_DFMT1_LK1_SHIFT (30U) 3505 #define RTU_XRDC_MDA_W4_11_DFMT1_LK1_WIDTH (1U) 3506 #define RTU_XRDC_MDA_W4_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_LK1_MASK) 3507 3508 #define RTU_XRDC_MDA_W4_11_DFMT1_VLD_MASK (0x80000000U) 3509 #define RTU_XRDC_MDA_W4_11_DFMT1_VLD_SHIFT (31U) 3510 #define RTU_XRDC_MDA_W4_11_DFMT1_VLD_WIDTH (1U) 3511 #define RTU_XRDC_MDA_W4_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W4_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W4_11_DFMT1_VLD_MASK) 3512 /*! @} */ 3513 3514 /*! @name MDA_W5_11_DFMT1 - Master Domain Assignment */ 3515 /*! @{ */ 3516 3517 #define RTU_XRDC_MDA_W5_11_DFMT1_DID_MASK (0xFU) 3518 #define RTU_XRDC_MDA_W5_11_DFMT1_DID_SHIFT (0U) 3519 #define RTU_XRDC_MDA_W5_11_DFMT1_DID_WIDTH (4U) 3520 #define RTU_XRDC_MDA_W5_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_DID_MASK) 3521 3522 #define RTU_XRDC_MDA_W5_11_DFMT1_PA_MASK (0x30U) 3523 #define RTU_XRDC_MDA_W5_11_DFMT1_PA_SHIFT (4U) 3524 #define RTU_XRDC_MDA_W5_11_DFMT1_PA_WIDTH (2U) 3525 #define RTU_XRDC_MDA_W5_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_PA_MASK) 3526 3527 #define RTU_XRDC_MDA_W5_11_DFMT1_SA_MASK (0xC0U) 3528 #define RTU_XRDC_MDA_W5_11_DFMT1_SA_SHIFT (6U) 3529 #define RTU_XRDC_MDA_W5_11_DFMT1_SA_WIDTH (2U) 3530 #define RTU_XRDC_MDA_W5_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_SA_MASK) 3531 3532 #define RTU_XRDC_MDA_W5_11_DFMT1_DIDB_MASK (0x100U) 3533 #define RTU_XRDC_MDA_W5_11_DFMT1_DIDB_SHIFT (8U) 3534 #define RTU_XRDC_MDA_W5_11_DFMT1_DIDB_WIDTH (1U) 3535 #define RTU_XRDC_MDA_W5_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_DIDB_MASK) 3536 3537 #define RTU_XRDC_MDA_W5_11_DFMT1_LPID_MASK (0xF000000U) 3538 #define RTU_XRDC_MDA_W5_11_DFMT1_LPID_SHIFT (24U) 3539 #define RTU_XRDC_MDA_W5_11_DFMT1_LPID_WIDTH (4U) 3540 #define RTU_XRDC_MDA_W5_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_LPID_MASK) 3541 3542 #define RTU_XRDC_MDA_W5_11_DFMT1_LPE_MASK (0x10000000U) 3543 #define RTU_XRDC_MDA_W5_11_DFMT1_LPE_SHIFT (28U) 3544 #define RTU_XRDC_MDA_W5_11_DFMT1_LPE_WIDTH (1U) 3545 #define RTU_XRDC_MDA_W5_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_LPE_MASK) 3546 3547 #define RTU_XRDC_MDA_W5_11_DFMT1_DFMT_MASK (0x20000000U) 3548 #define RTU_XRDC_MDA_W5_11_DFMT1_DFMT_SHIFT (29U) 3549 #define RTU_XRDC_MDA_W5_11_DFMT1_DFMT_WIDTH (1U) 3550 #define RTU_XRDC_MDA_W5_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_DFMT_MASK) 3551 3552 #define RTU_XRDC_MDA_W5_11_DFMT1_LK1_MASK (0x40000000U) 3553 #define RTU_XRDC_MDA_W5_11_DFMT1_LK1_SHIFT (30U) 3554 #define RTU_XRDC_MDA_W5_11_DFMT1_LK1_WIDTH (1U) 3555 #define RTU_XRDC_MDA_W5_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_LK1_MASK) 3556 3557 #define RTU_XRDC_MDA_W5_11_DFMT1_VLD_MASK (0x80000000U) 3558 #define RTU_XRDC_MDA_W5_11_DFMT1_VLD_SHIFT (31U) 3559 #define RTU_XRDC_MDA_W5_11_DFMT1_VLD_WIDTH (1U) 3560 #define RTU_XRDC_MDA_W5_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W5_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W5_11_DFMT1_VLD_MASK) 3561 /*! @} */ 3562 3563 /*! @name MDA_W6_11_DFMT1 - Master Domain Assignment */ 3564 /*! @{ */ 3565 3566 #define RTU_XRDC_MDA_W6_11_DFMT1_DID_MASK (0xFU) 3567 #define RTU_XRDC_MDA_W6_11_DFMT1_DID_SHIFT (0U) 3568 #define RTU_XRDC_MDA_W6_11_DFMT1_DID_WIDTH (4U) 3569 #define RTU_XRDC_MDA_W6_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_DID_MASK) 3570 3571 #define RTU_XRDC_MDA_W6_11_DFMT1_PA_MASK (0x30U) 3572 #define RTU_XRDC_MDA_W6_11_DFMT1_PA_SHIFT (4U) 3573 #define RTU_XRDC_MDA_W6_11_DFMT1_PA_WIDTH (2U) 3574 #define RTU_XRDC_MDA_W6_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_PA_MASK) 3575 3576 #define RTU_XRDC_MDA_W6_11_DFMT1_SA_MASK (0xC0U) 3577 #define RTU_XRDC_MDA_W6_11_DFMT1_SA_SHIFT (6U) 3578 #define RTU_XRDC_MDA_W6_11_DFMT1_SA_WIDTH (2U) 3579 #define RTU_XRDC_MDA_W6_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_SA_MASK) 3580 3581 #define RTU_XRDC_MDA_W6_11_DFMT1_DIDB_MASK (0x100U) 3582 #define RTU_XRDC_MDA_W6_11_DFMT1_DIDB_SHIFT (8U) 3583 #define RTU_XRDC_MDA_W6_11_DFMT1_DIDB_WIDTH (1U) 3584 #define RTU_XRDC_MDA_W6_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_DIDB_MASK) 3585 3586 #define RTU_XRDC_MDA_W6_11_DFMT1_LPID_MASK (0xF000000U) 3587 #define RTU_XRDC_MDA_W6_11_DFMT1_LPID_SHIFT (24U) 3588 #define RTU_XRDC_MDA_W6_11_DFMT1_LPID_WIDTH (4U) 3589 #define RTU_XRDC_MDA_W6_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_LPID_MASK) 3590 3591 #define RTU_XRDC_MDA_W6_11_DFMT1_LPE_MASK (0x10000000U) 3592 #define RTU_XRDC_MDA_W6_11_DFMT1_LPE_SHIFT (28U) 3593 #define RTU_XRDC_MDA_W6_11_DFMT1_LPE_WIDTH (1U) 3594 #define RTU_XRDC_MDA_W6_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_LPE_MASK) 3595 3596 #define RTU_XRDC_MDA_W6_11_DFMT1_DFMT_MASK (0x20000000U) 3597 #define RTU_XRDC_MDA_W6_11_DFMT1_DFMT_SHIFT (29U) 3598 #define RTU_XRDC_MDA_W6_11_DFMT1_DFMT_WIDTH (1U) 3599 #define RTU_XRDC_MDA_W6_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_DFMT_MASK) 3600 3601 #define RTU_XRDC_MDA_W6_11_DFMT1_LK1_MASK (0x40000000U) 3602 #define RTU_XRDC_MDA_W6_11_DFMT1_LK1_SHIFT (30U) 3603 #define RTU_XRDC_MDA_W6_11_DFMT1_LK1_WIDTH (1U) 3604 #define RTU_XRDC_MDA_W6_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_LK1_MASK) 3605 3606 #define RTU_XRDC_MDA_W6_11_DFMT1_VLD_MASK (0x80000000U) 3607 #define RTU_XRDC_MDA_W6_11_DFMT1_VLD_SHIFT (31U) 3608 #define RTU_XRDC_MDA_W6_11_DFMT1_VLD_WIDTH (1U) 3609 #define RTU_XRDC_MDA_W6_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W6_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W6_11_DFMT1_VLD_MASK) 3610 /*! @} */ 3611 3612 /*! @name MDA_W7_11_DFMT1 - Master Domain Assignment */ 3613 /*! @{ */ 3614 3615 #define RTU_XRDC_MDA_W7_11_DFMT1_DID_MASK (0xFU) 3616 #define RTU_XRDC_MDA_W7_11_DFMT1_DID_SHIFT (0U) 3617 #define RTU_XRDC_MDA_W7_11_DFMT1_DID_WIDTH (4U) 3618 #define RTU_XRDC_MDA_W7_11_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_DID_MASK) 3619 3620 #define RTU_XRDC_MDA_W7_11_DFMT1_PA_MASK (0x30U) 3621 #define RTU_XRDC_MDA_W7_11_DFMT1_PA_SHIFT (4U) 3622 #define RTU_XRDC_MDA_W7_11_DFMT1_PA_WIDTH (2U) 3623 #define RTU_XRDC_MDA_W7_11_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_PA_MASK) 3624 3625 #define RTU_XRDC_MDA_W7_11_DFMT1_SA_MASK (0xC0U) 3626 #define RTU_XRDC_MDA_W7_11_DFMT1_SA_SHIFT (6U) 3627 #define RTU_XRDC_MDA_W7_11_DFMT1_SA_WIDTH (2U) 3628 #define RTU_XRDC_MDA_W7_11_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_SA_MASK) 3629 3630 #define RTU_XRDC_MDA_W7_11_DFMT1_DIDB_MASK (0x100U) 3631 #define RTU_XRDC_MDA_W7_11_DFMT1_DIDB_SHIFT (8U) 3632 #define RTU_XRDC_MDA_W7_11_DFMT1_DIDB_WIDTH (1U) 3633 #define RTU_XRDC_MDA_W7_11_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_DIDB_MASK) 3634 3635 #define RTU_XRDC_MDA_W7_11_DFMT1_LPID_MASK (0xF000000U) 3636 #define RTU_XRDC_MDA_W7_11_DFMT1_LPID_SHIFT (24U) 3637 #define RTU_XRDC_MDA_W7_11_DFMT1_LPID_WIDTH (4U) 3638 #define RTU_XRDC_MDA_W7_11_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_LPID_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_LPID_MASK) 3639 3640 #define RTU_XRDC_MDA_W7_11_DFMT1_LPE_MASK (0x10000000U) 3641 #define RTU_XRDC_MDA_W7_11_DFMT1_LPE_SHIFT (28U) 3642 #define RTU_XRDC_MDA_W7_11_DFMT1_LPE_WIDTH (1U) 3643 #define RTU_XRDC_MDA_W7_11_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_LPE_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_LPE_MASK) 3644 3645 #define RTU_XRDC_MDA_W7_11_DFMT1_DFMT_MASK (0x20000000U) 3646 #define RTU_XRDC_MDA_W7_11_DFMT1_DFMT_SHIFT (29U) 3647 #define RTU_XRDC_MDA_W7_11_DFMT1_DFMT_WIDTH (1U) 3648 #define RTU_XRDC_MDA_W7_11_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_DFMT_MASK) 3649 3650 #define RTU_XRDC_MDA_W7_11_DFMT1_LK1_MASK (0x40000000U) 3651 #define RTU_XRDC_MDA_W7_11_DFMT1_LK1_SHIFT (30U) 3652 #define RTU_XRDC_MDA_W7_11_DFMT1_LK1_WIDTH (1U) 3653 #define RTU_XRDC_MDA_W7_11_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_LK1_MASK) 3654 3655 #define RTU_XRDC_MDA_W7_11_DFMT1_VLD_MASK (0x80000000U) 3656 #define RTU_XRDC_MDA_W7_11_DFMT1_VLD_SHIFT (31U) 3657 #define RTU_XRDC_MDA_W7_11_DFMT1_VLD_WIDTH (1U) 3658 #define RTU_XRDC_MDA_W7_11_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W7_11_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W7_11_DFMT1_VLD_MASK) 3659 /*! @} */ 3660 3661 /*! @name MDA_W0_12_DFMT1 - Master Domain Assignment */ 3662 /*! @{ */ 3663 3664 #define RTU_XRDC_MDA_W0_12_DFMT1_DID_MASK (0xFU) 3665 #define RTU_XRDC_MDA_W0_12_DFMT1_DID_SHIFT (0U) 3666 #define RTU_XRDC_MDA_W0_12_DFMT1_DID_WIDTH (4U) 3667 #define RTU_XRDC_MDA_W0_12_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_DID_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_DID_MASK) 3668 3669 #define RTU_XRDC_MDA_W0_12_DFMT1_PA_MASK (0x30U) 3670 #define RTU_XRDC_MDA_W0_12_DFMT1_PA_SHIFT (4U) 3671 #define RTU_XRDC_MDA_W0_12_DFMT1_PA_WIDTH (2U) 3672 #define RTU_XRDC_MDA_W0_12_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_PA_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_PA_MASK) 3673 3674 #define RTU_XRDC_MDA_W0_12_DFMT1_SA_MASK (0xC0U) 3675 #define RTU_XRDC_MDA_W0_12_DFMT1_SA_SHIFT (6U) 3676 #define RTU_XRDC_MDA_W0_12_DFMT1_SA_WIDTH (2U) 3677 #define RTU_XRDC_MDA_W0_12_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_SA_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_SA_MASK) 3678 3679 #define RTU_XRDC_MDA_W0_12_DFMT1_DIDB_MASK (0x100U) 3680 #define RTU_XRDC_MDA_W0_12_DFMT1_DIDB_SHIFT (8U) 3681 #define RTU_XRDC_MDA_W0_12_DFMT1_DIDB_WIDTH (1U) 3682 #define RTU_XRDC_MDA_W0_12_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_DIDB_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_DIDB_MASK) 3683 3684 #define RTU_XRDC_MDA_W0_12_DFMT1_DFMT_MASK (0x20000000U) 3685 #define RTU_XRDC_MDA_W0_12_DFMT1_DFMT_SHIFT (29U) 3686 #define RTU_XRDC_MDA_W0_12_DFMT1_DFMT_WIDTH (1U) 3687 #define RTU_XRDC_MDA_W0_12_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_DFMT_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_DFMT_MASK) 3688 3689 #define RTU_XRDC_MDA_W0_12_DFMT1_LK1_MASK (0x40000000U) 3690 #define RTU_XRDC_MDA_W0_12_DFMT1_LK1_SHIFT (30U) 3691 #define RTU_XRDC_MDA_W0_12_DFMT1_LK1_WIDTH (1U) 3692 #define RTU_XRDC_MDA_W0_12_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_LK1_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_LK1_MASK) 3693 3694 #define RTU_XRDC_MDA_W0_12_DFMT1_VLD_MASK (0x80000000U) 3695 #define RTU_XRDC_MDA_W0_12_DFMT1_VLD_SHIFT (31U) 3696 #define RTU_XRDC_MDA_W0_12_DFMT1_VLD_WIDTH (1U) 3697 #define RTU_XRDC_MDA_W0_12_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_MDA_W0_12_DFMT1_VLD_SHIFT)) & RTU_XRDC_MDA_W0_12_DFMT1_VLD_MASK) 3698 /*! @} */ 3699 3700 /*! @name PDAC_W0 - Peripheral Domain Access Control Word 0 */ 3701 /*! @{ */ 3702 3703 #define RTU_XRDC_PDAC_W0_D0ACP_MASK (0x7U) 3704 #define RTU_XRDC_PDAC_W0_D0ACP_SHIFT (0U) 3705 #define RTU_XRDC_PDAC_W0_D0ACP_WIDTH (3U) 3706 #define RTU_XRDC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D0ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D0ACP_MASK) 3707 3708 #define RTU_XRDC_PDAC_W0_D1ACP_MASK (0x38U) 3709 #define RTU_XRDC_PDAC_W0_D1ACP_SHIFT (3U) 3710 #define RTU_XRDC_PDAC_W0_D1ACP_WIDTH (3U) 3711 #define RTU_XRDC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D1ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D1ACP_MASK) 3712 3713 #define RTU_XRDC_PDAC_W0_D2ACP_MASK (0x1C0U) 3714 #define RTU_XRDC_PDAC_W0_D2ACP_SHIFT (6U) 3715 #define RTU_XRDC_PDAC_W0_D2ACP_WIDTH (3U) 3716 #define RTU_XRDC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D2ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D2ACP_MASK) 3717 3718 #define RTU_XRDC_PDAC_W0_D3ACP_MASK (0xE00U) 3719 #define RTU_XRDC_PDAC_W0_D3ACP_SHIFT (9U) 3720 #define RTU_XRDC_PDAC_W0_D3ACP_WIDTH (3U) 3721 #define RTU_XRDC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D3ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D3ACP_MASK) 3722 3723 #define RTU_XRDC_PDAC_W0_D4ACP_MASK (0x7000U) 3724 #define RTU_XRDC_PDAC_W0_D4ACP_SHIFT (12U) 3725 #define RTU_XRDC_PDAC_W0_D4ACP_WIDTH (3U) 3726 #define RTU_XRDC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D4ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D4ACP_MASK) 3727 3728 #define RTU_XRDC_PDAC_W0_D5ACP_MASK (0x38000U) 3729 #define RTU_XRDC_PDAC_W0_D5ACP_SHIFT (15U) 3730 #define RTU_XRDC_PDAC_W0_D5ACP_WIDTH (3U) 3731 #define RTU_XRDC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D5ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D5ACP_MASK) 3732 3733 #define RTU_XRDC_PDAC_W0_D6ACP_MASK (0x1C0000U) 3734 #define RTU_XRDC_PDAC_W0_D6ACP_SHIFT (18U) 3735 #define RTU_XRDC_PDAC_W0_D6ACP_WIDTH (3U) 3736 #define RTU_XRDC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D6ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D6ACP_MASK) 3737 3738 #define RTU_XRDC_PDAC_W0_D7ACP_MASK (0xE00000U) 3739 #define RTU_XRDC_PDAC_W0_D7ACP_SHIFT (21U) 3740 #define RTU_XRDC_PDAC_W0_D7ACP_WIDTH (3U) 3741 #define RTU_XRDC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_D7ACP_SHIFT)) & RTU_XRDC_PDAC_W0_D7ACP_MASK) 3742 3743 #define RTU_XRDC_PDAC_W0_SNUM_MASK (0xF000000U) 3744 #define RTU_XRDC_PDAC_W0_SNUM_SHIFT (24U) 3745 #define RTU_XRDC_PDAC_W0_SNUM_WIDTH (4U) 3746 #define RTU_XRDC_PDAC_W0_SNUM(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_SNUM_SHIFT)) & RTU_XRDC_PDAC_W0_SNUM_MASK) 3747 3748 #define RTU_XRDC_PDAC_W0_SE_MASK (0x40000000U) 3749 #define RTU_XRDC_PDAC_W0_SE_SHIFT (30U) 3750 #define RTU_XRDC_PDAC_W0_SE_WIDTH (1U) 3751 #define RTU_XRDC_PDAC_W0_SE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W0_SE_SHIFT)) & RTU_XRDC_PDAC_W0_SE_MASK) 3752 /*! @} */ 3753 3754 /*! @name PDAC_W1 - Peripheral Domain Access Control Word 1 */ 3755 /*! @{ */ 3756 3757 #define RTU_XRDC_PDAC_W1_D8ACP_MASK (0x7U) 3758 #define RTU_XRDC_PDAC_W1_D8ACP_SHIFT (0U) 3759 #define RTU_XRDC_PDAC_W1_D8ACP_WIDTH (3U) 3760 #define RTU_XRDC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D8ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D8ACP_MASK) 3761 3762 #define RTU_XRDC_PDAC_W1_D9ACP_MASK (0x38U) 3763 #define RTU_XRDC_PDAC_W1_D9ACP_SHIFT (3U) 3764 #define RTU_XRDC_PDAC_W1_D9ACP_WIDTH (3U) 3765 #define RTU_XRDC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D9ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D9ACP_MASK) 3766 3767 #define RTU_XRDC_PDAC_W1_D10ACP_MASK (0x1C0U) 3768 #define RTU_XRDC_PDAC_W1_D10ACP_SHIFT (6U) 3769 #define RTU_XRDC_PDAC_W1_D10ACP_WIDTH (3U) 3770 #define RTU_XRDC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D10ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D10ACP_MASK) 3771 3772 #define RTU_XRDC_PDAC_W1_D11ACP_MASK (0xE00U) 3773 #define RTU_XRDC_PDAC_W1_D11ACP_SHIFT (9U) 3774 #define RTU_XRDC_PDAC_W1_D11ACP_WIDTH (3U) 3775 #define RTU_XRDC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D11ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D11ACP_MASK) 3776 3777 #define RTU_XRDC_PDAC_W1_D12ACP_MASK (0x7000U) 3778 #define RTU_XRDC_PDAC_W1_D12ACP_SHIFT (12U) 3779 #define RTU_XRDC_PDAC_W1_D12ACP_WIDTH (3U) 3780 #define RTU_XRDC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D12ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D12ACP_MASK) 3781 3782 #define RTU_XRDC_PDAC_W1_D13ACP_MASK (0x38000U) 3783 #define RTU_XRDC_PDAC_W1_D13ACP_SHIFT (15U) 3784 #define RTU_XRDC_PDAC_W1_D13ACP_WIDTH (3U) 3785 #define RTU_XRDC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D13ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D13ACP_MASK) 3786 3787 #define RTU_XRDC_PDAC_W1_D14ACP_MASK (0x1C0000U) 3788 #define RTU_XRDC_PDAC_W1_D14ACP_SHIFT (18U) 3789 #define RTU_XRDC_PDAC_W1_D14ACP_WIDTH (3U) 3790 #define RTU_XRDC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D14ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D14ACP_MASK) 3791 3792 #define RTU_XRDC_PDAC_W1_D15ACP_MASK (0xE00000U) 3793 #define RTU_XRDC_PDAC_W1_D15ACP_SHIFT (21U) 3794 #define RTU_XRDC_PDAC_W1_D15ACP_WIDTH (3U) 3795 #define RTU_XRDC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_D15ACP_SHIFT)) & RTU_XRDC_PDAC_W1_D15ACP_MASK) 3796 3797 #define RTU_XRDC_PDAC_W1_LK2_MASK (0x60000000U) 3798 #define RTU_XRDC_PDAC_W1_LK2_SHIFT (29U) 3799 #define RTU_XRDC_PDAC_W1_LK2_WIDTH (2U) 3800 #define RTU_XRDC_PDAC_W1_LK2(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_LK2_SHIFT)) & RTU_XRDC_PDAC_W1_LK2_MASK) 3801 3802 #define RTU_XRDC_PDAC_W1_VLD_MASK (0x80000000U) 3803 #define RTU_XRDC_PDAC_W1_VLD_SHIFT (31U) 3804 #define RTU_XRDC_PDAC_W1_VLD_WIDTH (1U) 3805 #define RTU_XRDC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_PDAC_W1_VLD_SHIFT)) & RTU_XRDC_PDAC_W1_VLD_MASK) 3806 /*! @} */ 3807 3808 /*! @name XRDC_MRGD_W0 - Memory Region Descriptor Word 0 */ 3809 /*! @{ */ 3810 3811 #define RTU_XRDC_XRDC_MRGD_W0_SRTADDR_MASK (0xFFFFFFE0U) 3812 #define RTU_XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT (5U) 3813 #define RTU_XRDC_XRDC_MRGD_W0_SRTADDR_WIDTH (27U) 3814 #define RTU_XRDC_XRDC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT)) & RTU_XRDC_XRDC_MRGD_W0_SRTADDR_MASK) 3815 /*! @} */ 3816 3817 /*! @name XRDC_MRGD_W1 - Memory Region Descriptor Word 1 */ 3818 /*! @{ */ 3819 3820 #define RTU_XRDC_XRDC_MRGD_W1_ENDADDR_MASK (0xFFFFFFE0U) 3821 #define RTU_XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT (5U) 3822 #define RTU_XRDC_XRDC_MRGD_W1_ENDADDR_WIDTH (27U) 3823 #define RTU_XRDC_XRDC_MRGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT)) & RTU_XRDC_XRDC_MRGD_W1_ENDADDR_MASK) 3824 /*! @} */ 3825 3826 /*! @name XRDC_MRGD_W2 - Memory Region Descriptor Word 2 */ 3827 /*! @{ */ 3828 3829 #define RTU_XRDC_XRDC_MRGD_W2_D0ACP_MASK (0x7U) 3830 #define RTU_XRDC_XRDC_MRGD_W2_D0ACP_SHIFT (0U) 3831 #define RTU_XRDC_XRDC_MRGD_W2_D0ACP_WIDTH (3U) 3832 #define RTU_XRDC_XRDC_MRGD_W2_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D0ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D0ACP_MASK) 3833 3834 #define RTU_XRDC_XRDC_MRGD_W2_D1ACP_MASK (0x38U) 3835 #define RTU_XRDC_XRDC_MRGD_W2_D1ACP_SHIFT (3U) 3836 #define RTU_XRDC_XRDC_MRGD_W2_D1ACP_WIDTH (3U) 3837 #define RTU_XRDC_XRDC_MRGD_W2_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D1ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D1ACP_MASK) 3838 3839 #define RTU_XRDC_XRDC_MRGD_W2_D2ACP_MASK (0x1C0U) 3840 #define RTU_XRDC_XRDC_MRGD_W2_D2ACP_SHIFT (6U) 3841 #define RTU_XRDC_XRDC_MRGD_W2_D2ACP_WIDTH (3U) 3842 #define RTU_XRDC_XRDC_MRGD_W2_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D2ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D2ACP_MASK) 3843 3844 #define RTU_XRDC_XRDC_MRGD_W2_D3ACP_MASK (0xE00U) 3845 #define RTU_XRDC_XRDC_MRGD_W2_D3ACP_SHIFT (9U) 3846 #define RTU_XRDC_XRDC_MRGD_W2_D3ACP_WIDTH (3U) 3847 #define RTU_XRDC_XRDC_MRGD_W2_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D3ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D3ACP_MASK) 3848 3849 #define RTU_XRDC_XRDC_MRGD_W2_D4ACP_MASK (0x7000U) 3850 #define RTU_XRDC_XRDC_MRGD_W2_D4ACP_SHIFT (12U) 3851 #define RTU_XRDC_XRDC_MRGD_W2_D4ACP_WIDTH (3U) 3852 #define RTU_XRDC_XRDC_MRGD_W2_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D4ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D4ACP_MASK) 3853 3854 #define RTU_XRDC_XRDC_MRGD_W2_D5ACP_MASK (0x38000U) 3855 #define RTU_XRDC_XRDC_MRGD_W2_D5ACP_SHIFT (15U) 3856 #define RTU_XRDC_XRDC_MRGD_W2_D5ACP_WIDTH (3U) 3857 #define RTU_XRDC_XRDC_MRGD_W2_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D5ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D5ACP_MASK) 3858 3859 #define RTU_XRDC_XRDC_MRGD_W2_D6ACP_MASK (0x1C0000U) 3860 #define RTU_XRDC_XRDC_MRGD_W2_D6ACP_SHIFT (18U) 3861 #define RTU_XRDC_XRDC_MRGD_W2_D6ACP_WIDTH (3U) 3862 #define RTU_XRDC_XRDC_MRGD_W2_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D6ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D6ACP_MASK) 3863 3864 #define RTU_XRDC_XRDC_MRGD_W2_D7ACP_MASK (0xE00000U) 3865 #define RTU_XRDC_XRDC_MRGD_W2_D7ACP_SHIFT (21U) 3866 #define RTU_XRDC_XRDC_MRGD_W2_D7ACP_WIDTH (3U) 3867 #define RTU_XRDC_XRDC_MRGD_W2_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_D7ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_D7ACP_MASK) 3868 3869 #define RTU_XRDC_XRDC_MRGD_W2_SNUM_MASK (0xF000000U) 3870 #define RTU_XRDC_XRDC_MRGD_W2_SNUM_SHIFT (24U) 3871 #define RTU_XRDC_XRDC_MRGD_W2_SNUM_WIDTH (4U) 3872 #define RTU_XRDC_XRDC_MRGD_W2_SNUM(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_SNUM_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_SNUM_MASK) 3873 3874 #define RTU_XRDC_XRDC_MRGD_W2_SE_MASK (0x40000000U) 3875 #define RTU_XRDC_XRDC_MRGD_W2_SE_SHIFT (30U) 3876 #define RTU_XRDC_XRDC_MRGD_W2_SE_WIDTH (1U) 3877 #define RTU_XRDC_XRDC_MRGD_W2_SE(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W2_SE_SHIFT)) & RTU_XRDC_XRDC_MRGD_W2_SE_MASK) 3878 /*! @} */ 3879 3880 /*! @name XRDC_MRGD_W3 - Memory Region Descriptor Word 3 */ 3881 /*! @{ */ 3882 3883 #define RTU_XRDC_XRDC_MRGD_W3_D8ACP_MASK (0x7U) 3884 #define RTU_XRDC_XRDC_MRGD_W3_D8ACP_SHIFT (0U) 3885 #define RTU_XRDC_XRDC_MRGD_W3_D8ACP_WIDTH (3U) 3886 #define RTU_XRDC_XRDC_MRGD_W3_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D8ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D8ACP_MASK) 3887 3888 #define RTU_XRDC_XRDC_MRGD_W3_D9ACP_MASK (0x38U) 3889 #define RTU_XRDC_XRDC_MRGD_W3_D9ACP_SHIFT (3U) 3890 #define RTU_XRDC_XRDC_MRGD_W3_D9ACP_WIDTH (3U) 3891 #define RTU_XRDC_XRDC_MRGD_W3_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D9ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D9ACP_MASK) 3892 3893 #define RTU_XRDC_XRDC_MRGD_W3_D10ACP_MASK (0x1C0U) 3894 #define RTU_XRDC_XRDC_MRGD_W3_D10ACP_SHIFT (6U) 3895 #define RTU_XRDC_XRDC_MRGD_W3_D10ACP_WIDTH (3U) 3896 #define RTU_XRDC_XRDC_MRGD_W3_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D10ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D10ACP_MASK) 3897 3898 #define RTU_XRDC_XRDC_MRGD_W3_D11ACP_MASK (0xE00U) 3899 #define RTU_XRDC_XRDC_MRGD_W3_D11ACP_SHIFT (9U) 3900 #define RTU_XRDC_XRDC_MRGD_W3_D11ACP_WIDTH (3U) 3901 #define RTU_XRDC_XRDC_MRGD_W3_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D11ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D11ACP_MASK) 3902 3903 #define RTU_XRDC_XRDC_MRGD_W3_D12ACP_MASK (0x7000U) 3904 #define RTU_XRDC_XRDC_MRGD_W3_D12ACP_SHIFT (12U) 3905 #define RTU_XRDC_XRDC_MRGD_W3_D12ACP_WIDTH (3U) 3906 #define RTU_XRDC_XRDC_MRGD_W3_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D12ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D12ACP_MASK) 3907 3908 #define RTU_XRDC_XRDC_MRGD_W3_D13ACP_MASK (0x38000U) 3909 #define RTU_XRDC_XRDC_MRGD_W3_D13ACP_SHIFT (15U) 3910 #define RTU_XRDC_XRDC_MRGD_W3_D13ACP_WIDTH (3U) 3911 #define RTU_XRDC_XRDC_MRGD_W3_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D13ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D13ACP_MASK) 3912 3913 #define RTU_XRDC_XRDC_MRGD_W3_D14ACP_MASK (0x1C0000U) 3914 #define RTU_XRDC_XRDC_MRGD_W3_D14ACP_SHIFT (18U) 3915 #define RTU_XRDC_XRDC_MRGD_W3_D14ACP_WIDTH (3U) 3916 #define RTU_XRDC_XRDC_MRGD_W3_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D14ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D14ACP_MASK) 3917 3918 #define RTU_XRDC_XRDC_MRGD_W3_D15ACP_MASK (0xE00000U) 3919 #define RTU_XRDC_XRDC_MRGD_W3_D15ACP_SHIFT (21U) 3920 #define RTU_XRDC_XRDC_MRGD_W3_D15ACP_WIDTH (3U) 3921 #define RTU_XRDC_XRDC_MRGD_W3_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_D15ACP_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_D15ACP_MASK) 3922 3923 #define RTU_XRDC_XRDC_MRGD_W3_LK2_MASK (0x60000000U) 3924 #define RTU_XRDC_XRDC_MRGD_W3_LK2_SHIFT (29U) 3925 #define RTU_XRDC_XRDC_MRGD_W3_LK2_WIDTH (2U) 3926 #define RTU_XRDC_XRDC_MRGD_W3_LK2(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_LK2_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_LK2_MASK) 3927 3928 #define RTU_XRDC_XRDC_MRGD_W3_VLD_MASK (0x80000000U) 3929 #define RTU_XRDC_XRDC_MRGD_W3_VLD_SHIFT (31U) 3930 #define RTU_XRDC_XRDC_MRGD_W3_VLD_WIDTH (1U) 3931 #define RTU_XRDC_XRDC_MRGD_W3_VLD(x) (((uint32_t)(((uint32_t)(x)) << RTU_XRDC_XRDC_MRGD_W3_VLD_SHIFT)) & RTU_XRDC_XRDC_MRGD_W3_VLD_MASK) 3932 /*! @} */ 3933 3934 /*! 3935 * @} 3936 */ /* end of group RTU_XRDC_Register_Masks */ 3937 3938 /*! 3939 * @} 3940 */ /* end of group RTU_XRDC_Peripheral_Access_Layer */ 3941 3942 #endif /* #if !defined(S32Z2_RTU_XRDC_H_) */ 3943
