1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RTU_PMC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_RTU_PMC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RTU_PMC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RTU_PMC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTU_PMC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTU_PMC_Peripheral_Access_Layer RTU_PMC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTU_PMC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CTRL; /**< Main Control Register, offset: 0x0 */ 74 __IO uint32_t MCR; /**< Memory Control Register, offset: 0x4 */ 75 __IO uint32_t BER; /**< Byte Enable Register, offset: 0x8 */ 76 __IO uint32_t PCR; /**< Program Control Register, offset: 0xC */ 77 __I uint32_t RPR; /**< Read Pipeline Register, offset: 0x10 */ 78 __IO uint32_t STOPADDR; /**< Stop Address Register, offset: 0x14 */ 79 __IO uint32_t CADDR; /**< Column Address Register, offset: 0x18 */ 80 __IO uint32_t RADDR; /**< Row Address Register, offset: 0x1C */ 81 __IO uint32_t X0; /**< X Data Register 0, offset: 0x20 */ 82 __IO uint32_t X1; /**< X Data Register 1, offset: 0x24 */ 83 __IO uint32_t X2; /**< X Data Register 2, offset: 0x28 */ 84 __IO uint32_t X3; /**< X Data Register 3, offset: 0x2C */ 85 __IO uint32_t X4; /**< X Data Register 4, offset: 0x30 */ 86 __IO uint32_t X5; /**< X Data Register 5, offset: 0x34 */ 87 __IO uint32_t X6; /**< X Data Register 6, offset: 0x38 */ 88 __IO uint32_t X7; /**< X Data Register 7, offset: 0x3C */ 89 __IO uint32_t Y0; /**< Y Data Register 0, offset: 0x40 */ 90 __IO uint32_t Y1; /**< Y Data Register 1, offset: 0x44 */ 91 __IO uint32_t Y2; /**< Y Data Register 2, offset: 0x48 */ 92 __IO uint32_t Y3; /**< Y Data Register 3, offset: 0x4C */ 93 __IO uint32_t Y4; /**< Y Data Register 4, offset: 0x50 */ 94 __IO uint32_t Y5; /**< Y Data Register 5, offset: 0x54 */ 95 __IO uint32_t Y6; /**< Y Data Register 6, offset: 0x58 */ 96 __IO uint32_t Y7; /**< Y Data Register 7, offset: 0x5C */ 97 __IO uint32_t AIR; /**< Auxiliary Input Register, offset: 0x60 */ 98 __IO uint32_t AOR; /**< Auxiliary Output Register, offset: 0x64 */ 99 uint8_t RESERVED_0[24]; 100 __IO uint32_t DM0; /**< Data Mask Register 0, offset: 0x80 */ 101 __IO uint32_t DM1; /**< Data Mask Register 1, offset: 0x84 */ 102 __IO uint32_t DM2; /**< Data Mask Register 2, offset: 0x88 */ 103 __IO uint32_t DM3; /**< Data Mask Register 3, offset: 0x8C */ 104 __IO uint32_t DM4; /**< Data Mask Register 4, offset: 0x90 */ 105 __IO uint32_t DM5; /**< Data Mask Register 5, offset: 0x94 */ 106 __IO uint32_t DM6; /**< Data Mask Register 6, offset: 0x98 */ 107 __IO uint32_t DM7; /**< Data Mask Register 7, offset: 0x9C */ 108 uint8_t RESERVED_1[96]; 109 __IO uint32_t P0; /**< Program Register 0, offset: 0x100 */ 110 __IO uint32_t P1; /**< Program Register 1, offset: 0x104 */ 111 __IO uint32_t P2; /**< Program Register 2, offset: 0x108 */ 112 __IO uint32_t P3; /**< Program Register 3, offset: 0x10C */ 113 __IO uint32_t P4; /**< Program Register 4, offset: 0x110 */ 114 __IO uint32_t P5; /**< Program Register 5, offset: 0x114 */ 115 __IO uint32_t P6; /**< Program Register 6, offset: 0x118 */ 116 __IO uint32_t P7; /**< Program Register 7, offset: 0x11C */ 117 __IO uint32_t P8; /**< Program Register 8, offset: 0x120 */ 118 __IO uint32_t P9; /**< Program Register 9, offset: 0x124 */ 119 __IO uint32_t P10; /**< Program Register 10, offset: 0x128 */ 120 __IO uint32_t P11; /**< Program Register 11, offset: 0x12C */ 121 __IO uint32_t P12; /**< Program Register 12, offset: 0x130 */ 122 __IO uint32_t P13; /**< Program Register 13, offset: 0x134 */ 123 __IO uint32_t P14; /**< Program Register 14, offset: 0x138 */ 124 __IO uint32_t P15; /**< Program Register 15, offset: 0x13C */ 125 __IO uint32_t P16; /**< Program Register 16, offset: 0x140 */ 126 __IO uint32_t P17; /**< Program Register 17, offset: 0x144 */ 127 __IO uint32_t P18; /**< Program Register 18, offset: 0x148 */ 128 __IO uint32_t P19; /**< Program Register 19, offset: 0x14C */ 129 __IO uint32_t P20; /**< Program Register 20, offset: 0x150 */ 130 __IO uint32_t P21; /**< Program Register 21, offset: 0x154 */ 131 __IO uint32_t P22; /**< Program Register 22, offset: 0x158 */ 132 __IO uint32_t P23; /**< Program Register 23, offset: 0x15C */ 133 __IO uint32_t P24; /**< Program Register 24, offset: 0x160 */ 134 __IO uint32_t P25; /**< Program Register 25, offset: 0x164 */ 135 __IO uint32_t P26; /**< Program Register 26, offset: 0x168 */ 136 __IO uint32_t P27; /**< Program Register 27, offset: 0x16C */ 137 __IO uint32_t P28; /**< Program Register 28, offset: 0x170 */ 138 __IO uint32_t P29; /**< Program Register 29, offset: 0x174 */ 139 __IO uint32_t P30; /**< Program Register 30, offset: 0x178 */ 140 __IO uint32_t P31; /**< Program Register 31, offset: 0x17C */ 141 uint8_t RESERVED_2[3456]; 142 __I uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 143 uint8_t RESERVED_3[156]; 144 __IO uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ 145 __IO uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ 146 __I uint32_t DEVAFF0; /**< Device Affinity 0 Register, offset: 0xFA8 */ 147 __I uint32_t DEVAFF1; /**< Device Affinity 1 Register, offset: 0xFAC */ 148 uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */ 149 uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */ 150 uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ 151 __I uint32_t DEVARCH; /**< Device Architecture Register, offset: 0xFBC */ 152 uint32_t DEVID2; /**< Device ID Register 2, offset: 0xFC0 */ 153 uint32_t DEVID1; /**< Device ID Register 1, offset: 0xFC4 */ 154 uint32_t DEVID; /**< Device ID Register, offset: 0xFC8 */ 155 __I uint32_t DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ 156 __I uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ 157 uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ 158 uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ 159 uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ 160 __I uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ 161 __I uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ 162 __I uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ 163 __I uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ 164 __I uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ 165 __I uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ 166 __I uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ 167 __I uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ 168 } RTU_PMC_Type, *RTU_PMC_MemMapPtr; 169 170 /** Number of instances of the RTU_PMC module. */ 171 #define RTU_PMC_INSTANCE_COUNT (2u) 172 173 /* RTU_PMC - Peripheral instance base addresses */ 174 /** Peripheral RTU0__PMC base address */ 175 #define IP_RTU0__PMC_BASE (0x761B0000u) 176 /** Peripheral RTU0__PMC base pointer */ 177 #define IP_RTU0__PMC ((RTU_PMC_Type *)IP_RTU0__PMC_BASE) 178 /** Peripheral RTU1__PMC base address */ 179 #define IP_RTU1__PMC_BASE (0x769B0000u) 180 /** Peripheral RTU1__PMC base pointer */ 181 #define IP_RTU1__PMC ((RTU_PMC_Type *)IP_RTU1__PMC_BASE) 182 /** Array initializer of RTU_PMC peripheral base addresses */ 183 #define IP_RTU_PMC_BASE_ADDRS { IP_RTU0__PMC_BASE, IP_RTU1__PMC_BASE } 184 /** Array initializer of RTU_PMC peripheral base pointers */ 185 #define IP_RTU_PMC_BASE_PTRS { IP_RTU0__PMC, IP_RTU1__PMC } 186 187 /* ---------------------------------------------------------------------------- 188 -- RTU_PMC Register Masks 189 ---------------------------------------------------------------------------- */ 190 191 /*! 192 * @addtogroup RTU_PMC_Register_Masks RTU_PMC Register Masks 193 * @{ 194 */ 195 196 /*! @name CTRL - Main Control Register */ 197 /*! @{ */ 198 199 #define RTU_PMC_CTRL_PEEN_MASK (0x1U) 200 #define RTU_PMC_CTRL_PEEN_SHIFT (0U) 201 #define RTU_PMC_CTRL_PEEN_WIDTH (1U) 202 #define RTU_PMC_CTRL_PEEN(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_PEEN_SHIFT)) & RTU_PMC_CTRL_PEEN_MASK) 203 204 #define RTU_PMC_CTRL_PES_MASK (0x2U) 205 #define RTU_PMC_CTRL_PES_SHIFT (1U) 206 #define RTU_PMC_CTRL_PES_WIDTH (1U) 207 #define RTU_PMC_CTRL_PES(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_PES_SHIFT)) & RTU_PMC_CTRL_PES_MASK) 208 209 #define RTU_PMC_CTRL_TCSEN_MASK (0x4U) 210 #define RTU_PMC_CTRL_TCSEN_SHIFT (2U) 211 #define RTU_PMC_CTRL_TCSEN_WIDTH (1U) 212 #define RTU_PMC_CTRL_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TCSEN_SHIFT)) & RTU_PMC_CTRL_TCSEN_MASK) 213 214 #define RTU_PMC_CTRL_EXECO_MASK (0x8U) 215 #define RTU_PMC_CTRL_EXECO_SHIFT (3U) 216 #define RTU_PMC_CTRL_EXECO_WIDTH (1U) 217 #define RTU_PMC_CTRL_EXECO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_EXECO_SHIFT)) & RTU_PMC_CTRL_EXECO_MASK) 218 219 #define RTU_PMC_CTRL_STOPF_MASK (0x10U) 220 #define RTU_PMC_CTRL_STOPF_SHIFT (4U) 221 #define RTU_PMC_CTRL_STOPF_WIDTH (1U) 222 #define RTU_PMC_CTRL_STOPF(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_STOPF_SHIFT)) & RTU_PMC_CTRL_STOPF_MASK) 223 224 #define RTU_PMC_CTRL_TE_MASK (0x20U) 225 #define RTU_PMC_CTRL_TE_SHIFT (5U) 226 #define RTU_PMC_CTRL_TE_WIDTH (1U) 227 #define RTU_PMC_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TE_SHIFT)) & RTU_PMC_CTRL_TE_MASK) 228 229 #define RTU_PMC_CTRL_TESEN_MASK (0x40U) 230 #define RTU_PMC_CTRL_TESEN_SHIFT (6U) 231 #define RTU_PMC_CTRL_TESEN_WIDTH (1U) 232 #define RTU_PMC_CTRL_TESEN(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TESEN_SHIFT)) & RTU_PMC_CTRL_TESEN_MASK) 233 234 #define RTU_PMC_CTRL_TF_MASK (0x80U) 235 #define RTU_PMC_CTRL_TF_SHIFT (7U) 236 #define RTU_PMC_CTRL_TF_WIDTH (1U) 237 #define RTU_PMC_CTRL_TF(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TF_SHIFT)) & RTU_PMC_CTRL_TF_MASK) 238 239 #define RTU_PMC_CTRL_TFSEN_MASK (0x100U) 240 #define RTU_PMC_CTRL_TFSEN_SHIFT (8U) 241 #define RTU_PMC_CTRL_TFSEN_WIDTH (1U) 242 #define RTU_PMC_CTRL_TFSEN(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TFSEN_SHIFT)) & RTU_PMC_CTRL_TFSEN_MASK) 243 244 #define RTU_PMC_CTRL_ADDRCD_MASK (0x200U) 245 #define RTU_PMC_CTRL_ADDRCD_SHIFT (9U) 246 #define RTU_PMC_CTRL_ADDRCD_WIDTH (1U) 247 #define RTU_PMC_CTRL_ADDRCD(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_ADDRCD_SHIFT)) & RTU_PMC_CTRL_ADDRCD_MASK) 248 249 #define RTU_PMC_CTRL_ADDRID_MASK (0x400U) 250 #define RTU_PMC_CTRL_ADDRID_SHIFT (10U) 251 #define RTU_PMC_CTRL_ADDRID_WIDTH (1U) 252 #define RTU_PMC_CTRL_ADDRID(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_ADDRID_SHIFT)) & RTU_PMC_CTRL_ADDRID_MASK) 253 254 #define RTU_PMC_CTRL_TEN_MASK (0x800U) 255 #define RTU_PMC_CTRL_TEN_SHIFT (11U) 256 #define RTU_PMC_CTRL_TEN_WIDTH (1U) 257 #define RTU_PMC_CTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_TEN_SHIFT)) & RTU_PMC_CTRL_TEN_MASK) 258 259 #define RTU_PMC_CTRL_STATE_MASK (0x3000U) 260 #define RTU_PMC_CTRL_STATE_SHIFT (12U) 261 #define RTU_PMC_CTRL_STATE_WIDTH (2U) 262 #define RTU_PMC_CTRL_STATE(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_STATE_SHIFT)) & RTU_PMC_CTRL_STATE_MASK) 263 264 #define RTU_PMC_CTRL_MBISTACK_MASK (0x4000U) 265 #define RTU_PMC_CTRL_MBISTACK_SHIFT (14U) 266 #define RTU_PMC_CTRL_MBISTACK_WIDTH (1U) 267 #define RTU_PMC_CTRL_MBISTACK(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_MBISTACK_SHIFT)) & RTU_PMC_CTRL_MBISTACK_MASK) 268 269 #define RTU_PMC_CTRL_MBISTCFG_MASK (0xFFFF0000U) 270 #define RTU_PMC_CTRL_MBISTCFG_SHIFT (16U) 271 #define RTU_PMC_CTRL_MBISTCFG_WIDTH (16U) 272 #define RTU_PMC_CTRL_MBISTCFG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CTRL_MBISTCFG_SHIFT)) & RTU_PMC_CTRL_MBISTCFG_MASK) 273 /*! @} */ 274 275 /*! @name MCR - Memory Control Register */ 276 /*! @{ */ 277 278 #define RTU_PMC_MCR_ARRAY_MASK (0xFFU) 279 #define RTU_PMC_MCR_ARRAY_SHIFT (0U) 280 #define RTU_PMC_MCR_ARRAY_WIDTH (8U) 281 #define RTU_PMC_MCR_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_MCR_ARRAY_SHIFT)) & RTU_PMC_MCR_ARRAY_MASK) 282 283 #define RTU_PMC_MCR_PD_MASK (0x1F00U) 284 #define RTU_PMC_MCR_PD_SHIFT (8U) 285 #define RTU_PMC_MCR_PD_WIDTH (5U) 286 #define RTU_PMC_MCR_PD(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_MCR_PD_SHIFT)) & RTU_PMC_MCR_PD_MASK) 287 288 #define RTU_PMC_MCR_RCO_MASK (0x1E000U) 289 #define RTU_PMC_MCR_RCO_SHIFT (13U) 290 #define RTU_PMC_MCR_RCO_WIDTH (4U) 291 #define RTU_PMC_MCR_RCO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_MCR_RCO_SHIFT)) & RTU_PMC_MCR_RCO_MASK) 292 293 #define RTU_PMC_MCR_CCW_MASK (0x60000U) 294 #define RTU_PMC_MCR_CCW_SHIFT (17U) 295 #define RTU_PMC_MCR_CCW_WIDTH (2U) 296 #define RTU_PMC_MCR_CCW(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_MCR_CCW_SHIFT)) & RTU_PMC_MCR_CCW_MASK) 297 298 #define RTU_PMC_MCR_RCW_MASK (0x3E00000U) 299 #define RTU_PMC_MCR_RCW_SHIFT (21U) 300 #define RTU_PMC_MCR_RCW_WIDTH (5U) 301 #define RTU_PMC_MCR_RCW(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_MCR_RCW_SHIFT)) & RTU_PMC_MCR_RCW_MASK) 302 /*! @} */ 303 304 /*! @name BER - Byte Enable Register */ 305 /*! @{ */ 306 307 #define RTU_PMC_BER_BE_MASK (0xFFFFFFFFU) 308 #define RTU_PMC_BER_BE_SHIFT (0U) 309 #define RTU_PMC_BER_BE_WIDTH (32U) 310 #define RTU_PMC_BER_BE(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_BER_BE_SHIFT)) & RTU_PMC_BER_BE_MASK) 311 /*! @} */ 312 313 /*! @name PCR - Program Control Register */ 314 /*! @{ */ 315 316 #define RTU_PMC_PCR_PC_MASK (0x1FU) 317 #define RTU_PMC_PCR_PC_SHIFT (0U) 318 #define RTU_PMC_PCR_PC_WIDTH (5U) 319 #define RTU_PMC_PCR_PC(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PCR_PC_SHIFT)) & RTU_PMC_PCR_PC_MASK) 320 /*! @} */ 321 322 /*! @name RPR - Read Pipeline Register */ 323 /*! @{ */ 324 325 #define RTU_PMC_RPR_R_MASK (0xFFFFFFFFU) 326 #define RTU_PMC_RPR_R_SHIFT (0U) 327 #define RTU_PMC_RPR_R_WIDTH (32U) 328 #define RTU_PMC_RPR_R(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_RPR_R_SHIFT)) & RTU_PMC_RPR_R_MASK) 329 /*! @} */ 330 331 /*! @name STOPADDR - Stop Address Register */ 332 /*! @{ */ 333 334 #define RTU_PMC_STOPADDR_SA_MASK (0xFFFFFFFFU) 335 #define RTU_PMC_STOPADDR_SA_SHIFT (0U) 336 #define RTU_PMC_STOPADDR_SA_WIDTH (32U) 337 #define RTU_PMC_STOPADDR_SA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_STOPADDR_SA_SHIFT)) & RTU_PMC_STOPADDR_SA_MASK) 338 /*! @} */ 339 340 /*! @name CADDR - Column Address Register */ 341 /*! @{ */ 342 343 #define RTU_PMC_CADDR_CA_MASK (0x1FU) 344 #define RTU_PMC_CADDR_CA_SHIFT (0U) 345 #define RTU_PMC_CADDR_CA_WIDTH (5U) 346 #define RTU_PMC_CADDR_CA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CADDR_CA_SHIFT)) & RTU_PMC_CADDR_CA_MASK) 347 /*! @} */ 348 349 /*! @name RADDR - Row Address Register */ 350 /*! @{ */ 351 352 #define RTU_PMC_RADDR_RA_MASK (0x3FFFFFFFU) 353 #define RTU_PMC_RADDR_RA_SHIFT (0U) 354 #define RTU_PMC_RADDR_RA_WIDTH (30U) 355 #define RTU_PMC_RADDR_RA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_RADDR_RA_SHIFT)) & RTU_PMC_RADDR_RA_MASK) 356 /*! @} */ 357 358 /*! @name X0 - X Data Register 0 */ 359 /*! @{ */ 360 361 #define RTU_PMC_X0_X0_MASK (0xFFFFFFFFU) 362 #define RTU_PMC_X0_X0_SHIFT (0U) 363 #define RTU_PMC_X0_X0_WIDTH (32U) 364 #define RTU_PMC_X0_X0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X0_X0_SHIFT)) & RTU_PMC_X0_X0_MASK) 365 /*! @} */ 366 367 /*! @name X1 - X Data Register 1 */ 368 /*! @{ */ 369 370 #define RTU_PMC_X1_X1_MASK (0xFFFFFFFFU) 371 #define RTU_PMC_X1_X1_SHIFT (0U) 372 #define RTU_PMC_X1_X1_WIDTH (32U) 373 #define RTU_PMC_X1_X1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X1_X1_SHIFT)) & RTU_PMC_X1_X1_MASK) 374 /*! @} */ 375 376 /*! @name X2 - X Data Register 2 */ 377 /*! @{ */ 378 379 #define RTU_PMC_X2_X2_MASK (0xFFFFFFFFU) 380 #define RTU_PMC_X2_X2_SHIFT (0U) 381 #define RTU_PMC_X2_X2_WIDTH (32U) 382 #define RTU_PMC_X2_X2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X2_X2_SHIFT)) & RTU_PMC_X2_X2_MASK) 383 /*! @} */ 384 385 /*! @name X3 - X Data Register 3 */ 386 /*! @{ */ 387 388 #define RTU_PMC_X3_X3_MASK (0xFFFFFFFFU) 389 #define RTU_PMC_X3_X3_SHIFT (0U) 390 #define RTU_PMC_X3_X3_WIDTH (32U) 391 #define RTU_PMC_X3_X3(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X3_X3_SHIFT)) & RTU_PMC_X3_X3_MASK) 392 /*! @} */ 393 394 /*! @name X4 - X Data Register 4 */ 395 /*! @{ */ 396 397 #define RTU_PMC_X4_X4_MASK (0xFFFFFFFFU) 398 #define RTU_PMC_X4_X4_SHIFT (0U) 399 #define RTU_PMC_X4_X4_WIDTH (32U) 400 #define RTU_PMC_X4_X4(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X4_X4_SHIFT)) & RTU_PMC_X4_X4_MASK) 401 /*! @} */ 402 403 /*! @name X5 - X Data Register 5 */ 404 /*! @{ */ 405 406 #define RTU_PMC_X5_X5_MASK (0xFFFFFFFFU) 407 #define RTU_PMC_X5_X5_SHIFT (0U) 408 #define RTU_PMC_X5_X5_WIDTH (32U) 409 #define RTU_PMC_X5_X5(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X5_X5_SHIFT)) & RTU_PMC_X5_X5_MASK) 410 /*! @} */ 411 412 /*! @name X6 - X Data Register 6 */ 413 /*! @{ */ 414 415 #define RTU_PMC_X6_X6_MASK (0xFFFFFFFFU) 416 #define RTU_PMC_X6_X6_SHIFT (0U) 417 #define RTU_PMC_X6_X6_WIDTH (32U) 418 #define RTU_PMC_X6_X6(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X6_X6_SHIFT)) & RTU_PMC_X6_X6_MASK) 419 /*! @} */ 420 421 /*! @name X7 - X Data Register 7 */ 422 /*! @{ */ 423 424 #define RTU_PMC_X7_X7_MASK (0xFFFFFFFFU) 425 #define RTU_PMC_X7_X7_SHIFT (0U) 426 #define RTU_PMC_X7_X7_WIDTH (32U) 427 #define RTU_PMC_X7_X7(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_X7_X7_SHIFT)) & RTU_PMC_X7_X7_MASK) 428 /*! @} */ 429 430 /*! @name Y0 - Y Data Register 0 */ 431 /*! @{ */ 432 433 #define RTU_PMC_Y0_Y0_MASK (0xFFFFFFFFU) 434 #define RTU_PMC_Y0_Y0_SHIFT (0U) 435 #define RTU_PMC_Y0_Y0_WIDTH (32U) 436 #define RTU_PMC_Y0_Y0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y0_Y0_SHIFT)) & RTU_PMC_Y0_Y0_MASK) 437 /*! @} */ 438 439 /*! @name Y1 - Y Data Register 1 */ 440 /*! @{ */ 441 442 #define RTU_PMC_Y1_Y1_MASK (0xFFFFFFFFU) 443 #define RTU_PMC_Y1_Y1_SHIFT (0U) 444 #define RTU_PMC_Y1_Y1_WIDTH (32U) 445 #define RTU_PMC_Y1_Y1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y1_Y1_SHIFT)) & RTU_PMC_Y1_Y1_MASK) 446 /*! @} */ 447 448 /*! @name Y2 - Y Data Register 2 */ 449 /*! @{ */ 450 451 #define RTU_PMC_Y2_Y2_MASK (0xFFFFFFFFU) 452 #define RTU_PMC_Y2_Y2_SHIFT (0U) 453 #define RTU_PMC_Y2_Y2_WIDTH (32U) 454 #define RTU_PMC_Y2_Y2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y2_Y2_SHIFT)) & RTU_PMC_Y2_Y2_MASK) 455 /*! @} */ 456 457 /*! @name Y3 - Y Data Register 3 */ 458 /*! @{ */ 459 460 #define RTU_PMC_Y3_Y3_MASK (0xFFFFFFFFU) 461 #define RTU_PMC_Y3_Y3_SHIFT (0U) 462 #define RTU_PMC_Y3_Y3_WIDTH (32U) 463 #define RTU_PMC_Y3_Y3(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y3_Y3_SHIFT)) & RTU_PMC_Y3_Y3_MASK) 464 /*! @} */ 465 466 /*! @name Y4 - Y Data Register 4 */ 467 /*! @{ */ 468 469 #define RTU_PMC_Y4_Y4_MASK (0xFFFFFFFFU) 470 #define RTU_PMC_Y4_Y4_SHIFT (0U) 471 #define RTU_PMC_Y4_Y4_WIDTH (32U) 472 #define RTU_PMC_Y4_Y4(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y4_Y4_SHIFT)) & RTU_PMC_Y4_Y4_MASK) 473 /*! @} */ 474 475 /*! @name Y5 - Y Data Register 5 */ 476 /*! @{ */ 477 478 #define RTU_PMC_Y5_Y5_MASK (0xFFFFFFFFU) 479 #define RTU_PMC_Y5_Y5_SHIFT (0U) 480 #define RTU_PMC_Y5_Y5_WIDTH (32U) 481 #define RTU_PMC_Y5_Y5(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y5_Y5_SHIFT)) & RTU_PMC_Y5_Y5_MASK) 482 /*! @} */ 483 484 /*! @name Y6 - Y Data Register 6 */ 485 /*! @{ */ 486 487 #define RTU_PMC_Y6_Y6_MASK (0xFFFFFFFFU) 488 #define RTU_PMC_Y6_Y6_SHIFT (0U) 489 #define RTU_PMC_Y6_Y6_WIDTH (32U) 490 #define RTU_PMC_Y6_Y6(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y6_Y6_SHIFT)) & RTU_PMC_Y6_Y6_MASK) 491 /*! @} */ 492 493 /*! @name Y7 - Y Data Register 7 */ 494 /*! @{ */ 495 496 #define RTU_PMC_Y7_Y7_MASK (0xFFFFFFFFU) 497 #define RTU_PMC_Y7_Y7_SHIFT (0U) 498 #define RTU_PMC_Y7_Y7_WIDTH (32U) 499 #define RTU_PMC_Y7_Y7(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_Y7_Y7_SHIFT)) & RTU_PMC_Y7_Y7_MASK) 500 /*! @} */ 501 502 /*! @name AIR - Auxiliary Input Register */ 503 /*! @{ */ 504 505 #define RTU_PMC_AIR_AIR_MASK (0xFFFFFFFFU) 506 #define RTU_PMC_AIR_AIR_SHIFT (0U) 507 #define RTU_PMC_AIR_AIR_WIDTH (32U) 508 #define RTU_PMC_AIR_AIR(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_AIR_AIR_SHIFT)) & RTU_PMC_AIR_AIR_MASK) 509 /*! @} */ 510 511 /*! @name AOR - Auxiliary Output Register */ 512 /*! @{ */ 513 514 #define RTU_PMC_AOR_AOR_MASK (0xFFFFFFFFU) 515 #define RTU_PMC_AOR_AOR_SHIFT (0U) 516 #define RTU_PMC_AOR_AOR_WIDTH (32U) 517 #define RTU_PMC_AOR_AOR(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_AOR_AOR_SHIFT)) & RTU_PMC_AOR_AOR_MASK) 518 /*! @} */ 519 520 /*! @name DM0 - Data Mask Register 0 */ 521 /*! @{ */ 522 523 #define RTU_PMC_DM0_DM0_MASK (0xFFFFFFFFU) 524 #define RTU_PMC_DM0_DM0_SHIFT (0U) 525 #define RTU_PMC_DM0_DM0_WIDTH (32U) 526 #define RTU_PMC_DM0_DM0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM0_DM0_SHIFT)) & RTU_PMC_DM0_DM0_MASK) 527 /*! @} */ 528 529 /*! @name DM1 - Data Mask Register 1 */ 530 /*! @{ */ 531 532 #define RTU_PMC_DM1_DM1_MASK (0xFFFFFFFFU) 533 #define RTU_PMC_DM1_DM1_SHIFT (0U) 534 #define RTU_PMC_DM1_DM1_WIDTH (32U) 535 #define RTU_PMC_DM1_DM1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM1_DM1_SHIFT)) & RTU_PMC_DM1_DM1_MASK) 536 /*! @} */ 537 538 /*! @name DM2 - Data Mask Register 2 */ 539 /*! @{ */ 540 541 #define RTU_PMC_DM2_DM2_MASK (0xFFFFFFFFU) 542 #define RTU_PMC_DM2_DM2_SHIFT (0U) 543 #define RTU_PMC_DM2_DM2_WIDTH (32U) 544 #define RTU_PMC_DM2_DM2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM2_DM2_SHIFT)) & RTU_PMC_DM2_DM2_MASK) 545 /*! @} */ 546 547 /*! @name DM3 - Data Mask Register 3 */ 548 /*! @{ */ 549 550 #define RTU_PMC_DM3_DM3_MASK (0xFFFFFFFFU) 551 #define RTU_PMC_DM3_DM3_SHIFT (0U) 552 #define RTU_PMC_DM3_DM3_WIDTH (32U) 553 #define RTU_PMC_DM3_DM3(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM3_DM3_SHIFT)) & RTU_PMC_DM3_DM3_MASK) 554 /*! @} */ 555 556 /*! @name DM4 - Data Mask Register 4 */ 557 /*! @{ */ 558 559 #define RTU_PMC_DM4_DM4_MASK (0xFFFFFFFFU) 560 #define RTU_PMC_DM4_DM4_SHIFT (0U) 561 #define RTU_PMC_DM4_DM4_WIDTH (32U) 562 #define RTU_PMC_DM4_DM4(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM4_DM4_SHIFT)) & RTU_PMC_DM4_DM4_MASK) 563 /*! @} */ 564 565 /*! @name DM5 - Data Mask Register 5 */ 566 /*! @{ */ 567 568 #define RTU_PMC_DM5_DM5_MASK (0xFFFFFFFFU) 569 #define RTU_PMC_DM5_DM5_SHIFT (0U) 570 #define RTU_PMC_DM5_DM5_WIDTH (32U) 571 #define RTU_PMC_DM5_DM5(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM5_DM5_SHIFT)) & RTU_PMC_DM5_DM5_MASK) 572 /*! @} */ 573 574 /*! @name DM6 - Data Mask Register 6 */ 575 /*! @{ */ 576 577 #define RTU_PMC_DM6_DM6_MASK (0xFFFFFFFFU) 578 #define RTU_PMC_DM6_DM6_SHIFT (0U) 579 #define RTU_PMC_DM6_DM6_WIDTH (32U) 580 #define RTU_PMC_DM6_DM6(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM6_DM6_SHIFT)) & RTU_PMC_DM6_DM6_MASK) 581 /*! @} */ 582 583 /*! @name DM7 - Data Mask Register 7 */ 584 /*! @{ */ 585 586 #define RTU_PMC_DM7_DM7_MASK (0xFFFFFFFFU) 587 #define RTU_PMC_DM7_DM7_SHIFT (0U) 588 #define RTU_PMC_DM7_DM7_WIDTH (32U) 589 #define RTU_PMC_DM7_DM7(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DM7_DM7_SHIFT)) & RTU_PMC_DM7_DM7_MASK) 590 /*! @} */ 591 592 /*! @name P0 - Program Register 0 */ 593 /*! @{ */ 594 595 #define RTU_PMC_P0_OP_MASK (0x3U) 596 #define RTU_PMC_P0_OP_SHIFT (0U) 597 #define RTU_PMC_P0_OP_WIDTH (2U) 598 #define RTU_PMC_P0_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_OP_SHIFT)) & RTU_PMC_P0_OP_MASK) 599 600 #define RTU_PMC_P0_TRANS_MASK (0x30U) 601 #define RTU_PMC_P0_TRANS_SHIFT (4U) 602 #define RTU_PMC_P0_TRANS_WIDTH (2U) 603 #define RTU_PMC_P0_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_TRANS_SHIFT)) & RTU_PMC_P0_TRANS_MASK) 604 605 #define RTU_PMC_P0_DREG_MASK (0x40U) 606 #define RTU_PMC_P0_DREG_SHIFT (6U) 607 #define RTU_PMC_P0_DREG_WIDTH (1U) 608 #define RTU_PMC_P0_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_DREG_SHIFT)) & RTU_PMC_P0_DREG_MASK) 609 610 #define RTU_PMC_P0_DPOL_MASK (0x80U) 611 #define RTU_PMC_P0_DPOL_SHIFT (7U) 612 #define RTU_PMC_P0_DPOL_WIDTH (1U) 613 #define RTU_PMC_P0_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_DPOL_SHIFT)) & RTU_PMC_P0_DPOL_MASK) 614 615 #define RTU_PMC_P0_UA_MASK (0x100U) 616 #define RTU_PMC_P0_UA_SHIFT (8U) 617 #define RTU_PMC_P0_UA_WIDTH (1U) 618 #define RTU_PMC_P0_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_UA_SHIFT)) & RTU_PMC_P0_UA_MASK) 619 620 #define RTU_PMC_P0_AO_MASK (0x200U) 621 #define RTU_PMC_P0_AO_SHIFT (9U) 622 #define RTU_PMC_P0_AO_WIDTH (1U) 623 #define RTU_PMC_P0_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P0_AO_SHIFT)) & RTU_PMC_P0_AO_MASK) 624 /*! @} */ 625 626 /*! @name P1 - Program Register 1 */ 627 /*! @{ */ 628 629 #define RTU_PMC_P1_OP_MASK (0x3U) 630 #define RTU_PMC_P1_OP_SHIFT (0U) 631 #define RTU_PMC_P1_OP_WIDTH (2U) 632 #define RTU_PMC_P1_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_OP_SHIFT)) & RTU_PMC_P1_OP_MASK) 633 634 #define RTU_PMC_P1_TRANS_MASK (0x30U) 635 #define RTU_PMC_P1_TRANS_SHIFT (4U) 636 #define RTU_PMC_P1_TRANS_WIDTH (2U) 637 #define RTU_PMC_P1_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_TRANS_SHIFT)) & RTU_PMC_P1_TRANS_MASK) 638 639 #define RTU_PMC_P1_DREG_MASK (0x40U) 640 #define RTU_PMC_P1_DREG_SHIFT (6U) 641 #define RTU_PMC_P1_DREG_WIDTH (1U) 642 #define RTU_PMC_P1_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_DREG_SHIFT)) & RTU_PMC_P1_DREG_MASK) 643 644 #define RTU_PMC_P1_DPOL_MASK (0x80U) 645 #define RTU_PMC_P1_DPOL_SHIFT (7U) 646 #define RTU_PMC_P1_DPOL_WIDTH (1U) 647 #define RTU_PMC_P1_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_DPOL_SHIFT)) & RTU_PMC_P1_DPOL_MASK) 648 649 #define RTU_PMC_P1_UA_MASK (0x100U) 650 #define RTU_PMC_P1_UA_SHIFT (8U) 651 #define RTU_PMC_P1_UA_WIDTH (1U) 652 #define RTU_PMC_P1_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_UA_SHIFT)) & RTU_PMC_P1_UA_MASK) 653 654 #define RTU_PMC_P1_AO_MASK (0x200U) 655 #define RTU_PMC_P1_AO_SHIFT (9U) 656 #define RTU_PMC_P1_AO_WIDTH (1U) 657 #define RTU_PMC_P1_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P1_AO_SHIFT)) & RTU_PMC_P1_AO_MASK) 658 /*! @} */ 659 660 /*! @name P2 - Program Register 2 */ 661 /*! @{ */ 662 663 #define RTU_PMC_P2_OP_MASK (0x3U) 664 #define RTU_PMC_P2_OP_SHIFT (0U) 665 #define RTU_PMC_P2_OP_WIDTH (2U) 666 #define RTU_PMC_P2_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_OP_SHIFT)) & RTU_PMC_P2_OP_MASK) 667 668 #define RTU_PMC_P2_TRANS_MASK (0x30U) 669 #define RTU_PMC_P2_TRANS_SHIFT (4U) 670 #define RTU_PMC_P2_TRANS_WIDTH (2U) 671 #define RTU_PMC_P2_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_TRANS_SHIFT)) & RTU_PMC_P2_TRANS_MASK) 672 673 #define RTU_PMC_P2_DREG_MASK (0x40U) 674 #define RTU_PMC_P2_DREG_SHIFT (6U) 675 #define RTU_PMC_P2_DREG_WIDTH (1U) 676 #define RTU_PMC_P2_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_DREG_SHIFT)) & RTU_PMC_P2_DREG_MASK) 677 678 #define RTU_PMC_P2_DPOL_MASK (0x80U) 679 #define RTU_PMC_P2_DPOL_SHIFT (7U) 680 #define RTU_PMC_P2_DPOL_WIDTH (1U) 681 #define RTU_PMC_P2_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_DPOL_SHIFT)) & RTU_PMC_P2_DPOL_MASK) 682 683 #define RTU_PMC_P2_UA_MASK (0x100U) 684 #define RTU_PMC_P2_UA_SHIFT (8U) 685 #define RTU_PMC_P2_UA_WIDTH (1U) 686 #define RTU_PMC_P2_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_UA_SHIFT)) & RTU_PMC_P2_UA_MASK) 687 688 #define RTU_PMC_P2_AO_MASK (0x200U) 689 #define RTU_PMC_P2_AO_SHIFT (9U) 690 #define RTU_PMC_P2_AO_WIDTH (1U) 691 #define RTU_PMC_P2_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P2_AO_SHIFT)) & RTU_PMC_P2_AO_MASK) 692 /*! @} */ 693 694 /*! @name P3 - Program Register 3 */ 695 /*! @{ */ 696 697 #define RTU_PMC_P3_OP_MASK (0x3U) 698 #define RTU_PMC_P3_OP_SHIFT (0U) 699 #define RTU_PMC_P3_OP_WIDTH (2U) 700 #define RTU_PMC_P3_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_OP_SHIFT)) & RTU_PMC_P3_OP_MASK) 701 702 #define RTU_PMC_P3_TRANS_MASK (0x30U) 703 #define RTU_PMC_P3_TRANS_SHIFT (4U) 704 #define RTU_PMC_P3_TRANS_WIDTH (2U) 705 #define RTU_PMC_P3_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_TRANS_SHIFT)) & RTU_PMC_P3_TRANS_MASK) 706 707 #define RTU_PMC_P3_DREG_MASK (0x40U) 708 #define RTU_PMC_P3_DREG_SHIFT (6U) 709 #define RTU_PMC_P3_DREG_WIDTH (1U) 710 #define RTU_PMC_P3_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_DREG_SHIFT)) & RTU_PMC_P3_DREG_MASK) 711 712 #define RTU_PMC_P3_DPOL_MASK (0x80U) 713 #define RTU_PMC_P3_DPOL_SHIFT (7U) 714 #define RTU_PMC_P3_DPOL_WIDTH (1U) 715 #define RTU_PMC_P3_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_DPOL_SHIFT)) & RTU_PMC_P3_DPOL_MASK) 716 717 #define RTU_PMC_P3_UA_MASK (0x100U) 718 #define RTU_PMC_P3_UA_SHIFT (8U) 719 #define RTU_PMC_P3_UA_WIDTH (1U) 720 #define RTU_PMC_P3_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_UA_SHIFT)) & RTU_PMC_P3_UA_MASK) 721 722 #define RTU_PMC_P3_AO_MASK (0x200U) 723 #define RTU_PMC_P3_AO_SHIFT (9U) 724 #define RTU_PMC_P3_AO_WIDTH (1U) 725 #define RTU_PMC_P3_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P3_AO_SHIFT)) & RTU_PMC_P3_AO_MASK) 726 /*! @} */ 727 728 /*! @name P4 - Program Register 4 */ 729 /*! @{ */ 730 731 #define RTU_PMC_P4_OP_MASK (0x3U) 732 #define RTU_PMC_P4_OP_SHIFT (0U) 733 #define RTU_PMC_P4_OP_WIDTH (2U) 734 #define RTU_PMC_P4_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_OP_SHIFT)) & RTU_PMC_P4_OP_MASK) 735 736 #define RTU_PMC_P4_TRANS_MASK (0x30U) 737 #define RTU_PMC_P4_TRANS_SHIFT (4U) 738 #define RTU_PMC_P4_TRANS_WIDTH (2U) 739 #define RTU_PMC_P4_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_TRANS_SHIFT)) & RTU_PMC_P4_TRANS_MASK) 740 741 #define RTU_PMC_P4_DREG_MASK (0x40U) 742 #define RTU_PMC_P4_DREG_SHIFT (6U) 743 #define RTU_PMC_P4_DREG_WIDTH (1U) 744 #define RTU_PMC_P4_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_DREG_SHIFT)) & RTU_PMC_P4_DREG_MASK) 745 746 #define RTU_PMC_P4_DPOL_MASK (0x80U) 747 #define RTU_PMC_P4_DPOL_SHIFT (7U) 748 #define RTU_PMC_P4_DPOL_WIDTH (1U) 749 #define RTU_PMC_P4_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_DPOL_SHIFT)) & RTU_PMC_P4_DPOL_MASK) 750 751 #define RTU_PMC_P4_UA_MASK (0x100U) 752 #define RTU_PMC_P4_UA_SHIFT (8U) 753 #define RTU_PMC_P4_UA_WIDTH (1U) 754 #define RTU_PMC_P4_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_UA_SHIFT)) & RTU_PMC_P4_UA_MASK) 755 756 #define RTU_PMC_P4_AO_MASK (0x200U) 757 #define RTU_PMC_P4_AO_SHIFT (9U) 758 #define RTU_PMC_P4_AO_WIDTH (1U) 759 #define RTU_PMC_P4_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P4_AO_SHIFT)) & RTU_PMC_P4_AO_MASK) 760 /*! @} */ 761 762 /*! @name P5 - Program Register 5 */ 763 /*! @{ */ 764 765 #define RTU_PMC_P5_OP_MASK (0x3U) 766 #define RTU_PMC_P5_OP_SHIFT (0U) 767 #define RTU_PMC_P5_OP_WIDTH (2U) 768 #define RTU_PMC_P5_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_OP_SHIFT)) & RTU_PMC_P5_OP_MASK) 769 770 #define RTU_PMC_P5_TRANS_MASK (0x30U) 771 #define RTU_PMC_P5_TRANS_SHIFT (4U) 772 #define RTU_PMC_P5_TRANS_WIDTH (2U) 773 #define RTU_PMC_P5_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_TRANS_SHIFT)) & RTU_PMC_P5_TRANS_MASK) 774 775 #define RTU_PMC_P5_DREG_MASK (0x40U) 776 #define RTU_PMC_P5_DREG_SHIFT (6U) 777 #define RTU_PMC_P5_DREG_WIDTH (1U) 778 #define RTU_PMC_P5_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_DREG_SHIFT)) & RTU_PMC_P5_DREG_MASK) 779 780 #define RTU_PMC_P5_DPOL_MASK (0x80U) 781 #define RTU_PMC_P5_DPOL_SHIFT (7U) 782 #define RTU_PMC_P5_DPOL_WIDTH (1U) 783 #define RTU_PMC_P5_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_DPOL_SHIFT)) & RTU_PMC_P5_DPOL_MASK) 784 785 #define RTU_PMC_P5_UA_MASK (0x100U) 786 #define RTU_PMC_P5_UA_SHIFT (8U) 787 #define RTU_PMC_P5_UA_WIDTH (1U) 788 #define RTU_PMC_P5_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_UA_SHIFT)) & RTU_PMC_P5_UA_MASK) 789 790 #define RTU_PMC_P5_AO_MASK (0x200U) 791 #define RTU_PMC_P5_AO_SHIFT (9U) 792 #define RTU_PMC_P5_AO_WIDTH (1U) 793 #define RTU_PMC_P5_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P5_AO_SHIFT)) & RTU_PMC_P5_AO_MASK) 794 /*! @} */ 795 796 /*! @name P6 - Program Register 6 */ 797 /*! @{ */ 798 799 #define RTU_PMC_P6_OP_MASK (0x3U) 800 #define RTU_PMC_P6_OP_SHIFT (0U) 801 #define RTU_PMC_P6_OP_WIDTH (2U) 802 #define RTU_PMC_P6_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_OP_SHIFT)) & RTU_PMC_P6_OP_MASK) 803 804 #define RTU_PMC_P6_TRANS_MASK (0x30U) 805 #define RTU_PMC_P6_TRANS_SHIFT (4U) 806 #define RTU_PMC_P6_TRANS_WIDTH (2U) 807 #define RTU_PMC_P6_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_TRANS_SHIFT)) & RTU_PMC_P6_TRANS_MASK) 808 809 #define RTU_PMC_P6_DREG_MASK (0x40U) 810 #define RTU_PMC_P6_DREG_SHIFT (6U) 811 #define RTU_PMC_P6_DREG_WIDTH (1U) 812 #define RTU_PMC_P6_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_DREG_SHIFT)) & RTU_PMC_P6_DREG_MASK) 813 814 #define RTU_PMC_P6_DPOL_MASK (0x80U) 815 #define RTU_PMC_P6_DPOL_SHIFT (7U) 816 #define RTU_PMC_P6_DPOL_WIDTH (1U) 817 #define RTU_PMC_P6_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_DPOL_SHIFT)) & RTU_PMC_P6_DPOL_MASK) 818 819 #define RTU_PMC_P6_UA_MASK (0x100U) 820 #define RTU_PMC_P6_UA_SHIFT (8U) 821 #define RTU_PMC_P6_UA_WIDTH (1U) 822 #define RTU_PMC_P6_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_UA_SHIFT)) & RTU_PMC_P6_UA_MASK) 823 824 #define RTU_PMC_P6_AO_MASK (0x200U) 825 #define RTU_PMC_P6_AO_SHIFT (9U) 826 #define RTU_PMC_P6_AO_WIDTH (1U) 827 #define RTU_PMC_P6_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P6_AO_SHIFT)) & RTU_PMC_P6_AO_MASK) 828 /*! @} */ 829 830 /*! @name P7 - Program Register 7 */ 831 /*! @{ */ 832 833 #define RTU_PMC_P7_OP_MASK (0x3U) 834 #define RTU_PMC_P7_OP_SHIFT (0U) 835 #define RTU_PMC_P7_OP_WIDTH (2U) 836 #define RTU_PMC_P7_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_OP_SHIFT)) & RTU_PMC_P7_OP_MASK) 837 838 #define RTU_PMC_P7_TRANS_MASK (0x30U) 839 #define RTU_PMC_P7_TRANS_SHIFT (4U) 840 #define RTU_PMC_P7_TRANS_WIDTH (2U) 841 #define RTU_PMC_P7_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_TRANS_SHIFT)) & RTU_PMC_P7_TRANS_MASK) 842 843 #define RTU_PMC_P7_DREG_MASK (0x40U) 844 #define RTU_PMC_P7_DREG_SHIFT (6U) 845 #define RTU_PMC_P7_DREG_WIDTH (1U) 846 #define RTU_PMC_P7_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_DREG_SHIFT)) & RTU_PMC_P7_DREG_MASK) 847 848 #define RTU_PMC_P7_DPOL_MASK (0x80U) 849 #define RTU_PMC_P7_DPOL_SHIFT (7U) 850 #define RTU_PMC_P7_DPOL_WIDTH (1U) 851 #define RTU_PMC_P7_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_DPOL_SHIFT)) & RTU_PMC_P7_DPOL_MASK) 852 853 #define RTU_PMC_P7_UA_MASK (0x100U) 854 #define RTU_PMC_P7_UA_SHIFT (8U) 855 #define RTU_PMC_P7_UA_WIDTH (1U) 856 #define RTU_PMC_P7_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_UA_SHIFT)) & RTU_PMC_P7_UA_MASK) 857 858 #define RTU_PMC_P7_AO_MASK (0x200U) 859 #define RTU_PMC_P7_AO_SHIFT (9U) 860 #define RTU_PMC_P7_AO_WIDTH (1U) 861 #define RTU_PMC_P7_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P7_AO_SHIFT)) & RTU_PMC_P7_AO_MASK) 862 /*! @} */ 863 864 /*! @name P8 - Program Register 8 */ 865 /*! @{ */ 866 867 #define RTU_PMC_P8_OP_MASK (0x3U) 868 #define RTU_PMC_P8_OP_SHIFT (0U) 869 #define RTU_PMC_P8_OP_WIDTH (2U) 870 #define RTU_PMC_P8_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_OP_SHIFT)) & RTU_PMC_P8_OP_MASK) 871 872 #define RTU_PMC_P8_TRANS_MASK (0x30U) 873 #define RTU_PMC_P8_TRANS_SHIFT (4U) 874 #define RTU_PMC_P8_TRANS_WIDTH (2U) 875 #define RTU_PMC_P8_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_TRANS_SHIFT)) & RTU_PMC_P8_TRANS_MASK) 876 877 #define RTU_PMC_P8_DREG_MASK (0x40U) 878 #define RTU_PMC_P8_DREG_SHIFT (6U) 879 #define RTU_PMC_P8_DREG_WIDTH (1U) 880 #define RTU_PMC_P8_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_DREG_SHIFT)) & RTU_PMC_P8_DREG_MASK) 881 882 #define RTU_PMC_P8_DPOL_MASK (0x80U) 883 #define RTU_PMC_P8_DPOL_SHIFT (7U) 884 #define RTU_PMC_P8_DPOL_WIDTH (1U) 885 #define RTU_PMC_P8_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_DPOL_SHIFT)) & RTU_PMC_P8_DPOL_MASK) 886 887 #define RTU_PMC_P8_UA_MASK (0x100U) 888 #define RTU_PMC_P8_UA_SHIFT (8U) 889 #define RTU_PMC_P8_UA_WIDTH (1U) 890 #define RTU_PMC_P8_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_UA_SHIFT)) & RTU_PMC_P8_UA_MASK) 891 892 #define RTU_PMC_P8_AO_MASK (0x200U) 893 #define RTU_PMC_P8_AO_SHIFT (9U) 894 #define RTU_PMC_P8_AO_WIDTH (1U) 895 #define RTU_PMC_P8_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P8_AO_SHIFT)) & RTU_PMC_P8_AO_MASK) 896 /*! @} */ 897 898 /*! @name P9 - Program Register 9 */ 899 /*! @{ */ 900 901 #define RTU_PMC_P9_OP_MASK (0x3U) 902 #define RTU_PMC_P9_OP_SHIFT (0U) 903 #define RTU_PMC_P9_OP_WIDTH (2U) 904 #define RTU_PMC_P9_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_OP_SHIFT)) & RTU_PMC_P9_OP_MASK) 905 906 #define RTU_PMC_P9_TRANS_MASK (0x30U) 907 #define RTU_PMC_P9_TRANS_SHIFT (4U) 908 #define RTU_PMC_P9_TRANS_WIDTH (2U) 909 #define RTU_PMC_P9_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_TRANS_SHIFT)) & RTU_PMC_P9_TRANS_MASK) 910 911 #define RTU_PMC_P9_DREG_MASK (0x40U) 912 #define RTU_PMC_P9_DREG_SHIFT (6U) 913 #define RTU_PMC_P9_DREG_WIDTH (1U) 914 #define RTU_PMC_P9_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_DREG_SHIFT)) & RTU_PMC_P9_DREG_MASK) 915 916 #define RTU_PMC_P9_DPOL_MASK (0x80U) 917 #define RTU_PMC_P9_DPOL_SHIFT (7U) 918 #define RTU_PMC_P9_DPOL_WIDTH (1U) 919 #define RTU_PMC_P9_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_DPOL_SHIFT)) & RTU_PMC_P9_DPOL_MASK) 920 921 #define RTU_PMC_P9_UA_MASK (0x100U) 922 #define RTU_PMC_P9_UA_SHIFT (8U) 923 #define RTU_PMC_P9_UA_WIDTH (1U) 924 #define RTU_PMC_P9_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_UA_SHIFT)) & RTU_PMC_P9_UA_MASK) 925 926 #define RTU_PMC_P9_AO_MASK (0x200U) 927 #define RTU_PMC_P9_AO_SHIFT (9U) 928 #define RTU_PMC_P9_AO_WIDTH (1U) 929 #define RTU_PMC_P9_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P9_AO_SHIFT)) & RTU_PMC_P9_AO_MASK) 930 /*! @} */ 931 932 /*! @name P10 - Program Register 10 */ 933 /*! @{ */ 934 935 #define RTU_PMC_P10_OP_MASK (0x3U) 936 #define RTU_PMC_P10_OP_SHIFT (0U) 937 #define RTU_PMC_P10_OP_WIDTH (2U) 938 #define RTU_PMC_P10_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_OP_SHIFT)) & RTU_PMC_P10_OP_MASK) 939 940 #define RTU_PMC_P10_TRANS_MASK (0x30U) 941 #define RTU_PMC_P10_TRANS_SHIFT (4U) 942 #define RTU_PMC_P10_TRANS_WIDTH (2U) 943 #define RTU_PMC_P10_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_TRANS_SHIFT)) & RTU_PMC_P10_TRANS_MASK) 944 945 #define RTU_PMC_P10_DREG_MASK (0x40U) 946 #define RTU_PMC_P10_DREG_SHIFT (6U) 947 #define RTU_PMC_P10_DREG_WIDTH (1U) 948 #define RTU_PMC_P10_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_DREG_SHIFT)) & RTU_PMC_P10_DREG_MASK) 949 950 #define RTU_PMC_P10_DPOL_MASK (0x80U) 951 #define RTU_PMC_P10_DPOL_SHIFT (7U) 952 #define RTU_PMC_P10_DPOL_WIDTH (1U) 953 #define RTU_PMC_P10_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_DPOL_SHIFT)) & RTU_PMC_P10_DPOL_MASK) 954 955 #define RTU_PMC_P10_UA_MASK (0x100U) 956 #define RTU_PMC_P10_UA_SHIFT (8U) 957 #define RTU_PMC_P10_UA_WIDTH (1U) 958 #define RTU_PMC_P10_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_UA_SHIFT)) & RTU_PMC_P10_UA_MASK) 959 960 #define RTU_PMC_P10_AO_MASK (0x200U) 961 #define RTU_PMC_P10_AO_SHIFT (9U) 962 #define RTU_PMC_P10_AO_WIDTH (1U) 963 #define RTU_PMC_P10_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P10_AO_SHIFT)) & RTU_PMC_P10_AO_MASK) 964 /*! @} */ 965 966 /*! @name P11 - Program Register 11 */ 967 /*! @{ */ 968 969 #define RTU_PMC_P11_OP_MASK (0x3U) 970 #define RTU_PMC_P11_OP_SHIFT (0U) 971 #define RTU_PMC_P11_OP_WIDTH (2U) 972 #define RTU_PMC_P11_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_OP_SHIFT)) & RTU_PMC_P11_OP_MASK) 973 974 #define RTU_PMC_P11_TRANS_MASK (0x30U) 975 #define RTU_PMC_P11_TRANS_SHIFT (4U) 976 #define RTU_PMC_P11_TRANS_WIDTH (2U) 977 #define RTU_PMC_P11_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_TRANS_SHIFT)) & RTU_PMC_P11_TRANS_MASK) 978 979 #define RTU_PMC_P11_DREG_MASK (0x40U) 980 #define RTU_PMC_P11_DREG_SHIFT (6U) 981 #define RTU_PMC_P11_DREG_WIDTH (1U) 982 #define RTU_PMC_P11_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_DREG_SHIFT)) & RTU_PMC_P11_DREG_MASK) 983 984 #define RTU_PMC_P11_DPOL_MASK (0x80U) 985 #define RTU_PMC_P11_DPOL_SHIFT (7U) 986 #define RTU_PMC_P11_DPOL_WIDTH (1U) 987 #define RTU_PMC_P11_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_DPOL_SHIFT)) & RTU_PMC_P11_DPOL_MASK) 988 989 #define RTU_PMC_P11_UA_MASK (0x100U) 990 #define RTU_PMC_P11_UA_SHIFT (8U) 991 #define RTU_PMC_P11_UA_WIDTH (1U) 992 #define RTU_PMC_P11_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_UA_SHIFT)) & RTU_PMC_P11_UA_MASK) 993 994 #define RTU_PMC_P11_AO_MASK (0x200U) 995 #define RTU_PMC_P11_AO_SHIFT (9U) 996 #define RTU_PMC_P11_AO_WIDTH (1U) 997 #define RTU_PMC_P11_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P11_AO_SHIFT)) & RTU_PMC_P11_AO_MASK) 998 /*! @} */ 999 1000 /*! @name P12 - Program Register 12 */ 1001 /*! @{ */ 1002 1003 #define RTU_PMC_P12_OP_MASK (0x3U) 1004 #define RTU_PMC_P12_OP_SHIFT (0U) 1005 #define RTU_PMC_P12_OP_WIDTH (2U) 1006 #define RTU_PMC_P12_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_OP_SHIFT)) & RTU_PMC_P12_OP_MASK) 1007 1008 #define RTU_PMC_P12_TRANS_MASK (0x30U) 1009 #define RTU_PMC_P12_TRANS_SHIFT (4U) 1010 #define RTU_PMC_P12_TRANS_WIDTH (2U) 1011 #define RTU_PMC_P12_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_TRANS_SHIFT)) & RTU_PMC_P12_TRANS_MASK) 1012 1013 #define RTU_PMC_P12_DREG_MASK (0x40U) 1014 #define RTU_PMC_P12_DREG_SHIFT (6U) 1015 #define RTU_PMC_P12_DREG_WIDTH (1U) 1016 #define RTU_PMC_P12_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_DREG_SHIFT)) & RTU_PMC_P12_DREG_MASK) 1017 1018 #define RTU_PMC_P12_DPOL_MASK (0x80U) 1019 #define RTU_PMC_P12_DPOL_SHIFT (7U) 1020 #define RTU_PMC_P12_DPOL_WIDTH (1U) 1021 #define RTU_PMC_P12_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_DPOL_SHIFT)) & RTU_PMC_P12_DPOL_MASK) 1022 1023 #define RTU_PMC_P12_UA_MASK (0x100U) 1024 #define RTU_PMC_P12_UA_SHIFT (8U) 1025 #define RTU_PMC_P12_UA_WIDTH (1U) 1026 #define RTU_PMC_P12_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_UA_SHIFT)) & RTU_PMC_P12_UA_MASK) 1027 1028 #define RTU_PMC_P12_AO_MASK (0x200U) 1029 #define RTU_PMC_P12_AO_SHIFT (9U) 1030 #define RTU_PMC_P12_AO_WIDTH (1U) 1031 #define RTU_PMC_P12_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P12_AO_SHIFT)) & RTU_PMC_P12_AO_MASK) 1032 /*! @} */ 1033 1034 /*! @name P13 - Program Register 13 */ 1035 /*! @{ */ 1036 1037 #define RTU_PMC_P13_OP_MASK (0x3U) 1038 #define RTU_PMC_P13_OP_SHIFT (0U) 1039 #define RTU_PMC_P13_OP_WIDTH (2U) 1040 #define RTU_PMC_P13_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_OP_SHIFT)) & RTU_PMC_P13_OP_MASK) 1041 1042 #define RTU_PMC_P13_TRANS_MASK (0x30U) 1043 #define RTU_PMC_P13_TRANS_SHIFT (4U) 1044 #define RTU_PMC_P13_TRANS_WIDTH (2U) 1045 #define RTU_PMC_P13_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_TRANS_SHIFT)) & RTU_PMC_P13_TRANS_MASK) 1046 1047 #define RTU_PMC_P13_DREG_MASK (0x40U) 1048 #define RTU_PMC_P13_DREG_SHIFT (6U) 1049 #define RTU_PMC_P13_DREG_WIDTH (1U) 1050 #define RTU_PMC_P13_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_DREG_SHIFT)) & RTU_PMC_P13_DREG_MASK) 1051 1052 #define RTU_PMC_P13_DPOL_MASK (0x80U) 1053 #define RTU_PMC_P13_DPOL_SHIFT (7U) 1054 #define RTU_PMC_P13_DPOL_WIDTH (1U) 1055 #define RTU_PMC_P13_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_DPOL_SHIFT)) & RTU_PMC_P13_DPOL_MASK) 1056 1057 #define RTU_PMC_P13_UA_MASK (0x100U) 1058 #define RTU_PMC_P13_UA_SHIFT (8U) 1059 #define RTU_PMC_P13_UA_WIDTH (1U) 1060 #define RTU_PMC_P13_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_UA_SHIFT)) & RTU_PMC_P13_UA_MASK) 1061 1062 #define RTU_PMC_P13_AO_MASK (0x200U) 1063 #define RTU_PMC_P13_AO_SHIFT (9U) 1064 #define RTU_PMC_P13_AO_WIDTH (1U) 1065 #define RTU_PMC_P13_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P13_AO_SHIFT)) & RTU_PMC_P13_AO_MASK) 1066 /*! @} */ 1067 1068 /*! @name P14 - Program Register 14 */ 1069 /*! @{ */ 1070 1071 #define RTU_PMC_P14_OP_MASK (0x3U) 1072 #define RTU_PMC_P14_OP_SHIFT (0U) 1073 #define RTU_PMC_P14_OP_WIDTH (2U) 1074 #define RTU_PMC_P14_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_OP_SHIFT)) & RTU_PMC_P14_OP_MASK) 1075 1076 #define RTU_PMC_P14_TRANS_MASK (0x30U) 1077 #define RTU_PMC_P14_TRANS_SHIFT (4U) 1078 #define RTU_PMC_P14_TRANS_WIDTH (2U) 1079 #define RTU_PMC_P14_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_TRANS_SHIFT)) & RTU_PMC_P14_TRANS_MASK) 1080 1081 #define RTU_PMC_P14_DREG_MASK (0x40U) 1082 #define RTU_PMC_P14_DREG_SHIFT (6U) 1083 #define RTU_PMC_P14_DREG_WIDTH (1U) 1084 #define RTU_PMC_P14_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_DREG_SHIFT)) & RTU_PMC_P14_DREG_MASK) 1085 1086 #define RTU_PMC_P14_DPOL_MASK (0x80U) 1087 #define RTU_PMC_P14_DPOL_SHIFT (7U) 1088 #define RTU_PMC_P14_DPOL_WIDTH (1U) 1089 #define RTU_PMC_P14_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_DPOL_SHIFT)) & RTU_PMC_P14_DPOL_MASK) 1090 1091 #define RTU_PMC_P14_UA_MASK (0x100U) 1092 #define RTU_PMC_P14_UA_SHIFT (8U) 1093 #define RTU_PMC_P14_UA_WIDTH (1U) 1094 #define RTU_PMC_P14_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_UA_SHIFT)) & RTU_PMC_P14_UA_MASK) 1095 1096 #define RTU_PMC_P14_AO_MASK (0x200U) 1097 #define RTU_PMC_P14_AO_SHIFT (9U) 1098 #define RTU_PMC_P14_AO_WIDTH (1U) 1099 #define RTU_PMC_P14_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P14_AO_SHIFT)) & RTU_PMC_P14_AO_MASK) 1100 /*! @} */ 1101 1102 /*! @name P15 - Program Register 15 */ 1103 /*! @{ */ 1104 1105 #define RTU_PMC_P15_OP_MASK (0x3U) 1106 #define RTU_PMC_P15_OP_SHIFT (0U) 1107 #define RTU_PMC_P15_OP_WIDTH (2U) 1108 #define RTU_PMC_P15_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_OP_SHIFT)) & RTU_PMC_P15_OP_MASK) 1109 1110 #define RTU_PMC_P15_TRANS_MASK (0x30U) 1111 #define RTU_PMC_P15_TRANS_SHIFT (4U) 1112 #define RTU_PMC_P15_TRANS_WIDTH (2U) 1113 #define RTU_PMC_P15_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_TRANS_SHIFT)) & RTU_PMC_P15_TRANS_MASK) 1114 1115 #define RTU_PMC_P15_DREG_MASK (0x40U) 1116 #define RTU_PMC_P15_DREG_SHIFT (6U) 1117 #define RTU_PMC_P15_DREG_WIDTH (1U) 1118 #define RTU_PMC_P15_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_DREG_SHIFT)) & RTU_PMC_P15_DREG_MASK) 1119 1120 #define RTU_PMC_P15_DPOL_MASK (0x80U) 1121 #define RTU_PMC_P15_DPOL_SHIFT (7U) 1122 #define RTU_PMC_P15_DPOL_WIDTH (1U) 1123 #define RTU_PMC_P15_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_DPOL_SHIFT)) & RTU_PMC_P15_DPOL_MASK) 1124 1125 #define RTU_PMC_P15_UA_MASK (0x100U) 1126 #define RTU_PMC_P15_UA_SHIFT (8U) 1127 #define RTU_PMC_P15_UA_WIDTH (1U) 1128 #define RTU_PMC_P15_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_UA_SHIFT)) & RTU_PMC_P15_UA_MASK) 1129 1130 #define RTU_PMC_P15_AO_MASK (0x200U) 1131 #define RTU_PMC_P15_AO_SHIFT (9U) 1132 #define RTU_PMC_P15_AO_WIDTH (1U) 1133 #define RTU_PMC_P15_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P15_AO_SHIFT)) & RTU_PMC_P15_AO_MASK) 1134 /*! @} */ 1135 1136 /*! @name P16 - Program Register 16 */ 1137 /*! @{ */ 1138 1139 #define RTU_PMC_P16_OP_MASK (0x3U) 1140 #define RTU_PMC_P16_OP_SHIFT (0U) 1141 #define RTU_PMC_P16_OP_WIDTH (2U) 1142 #define RTU_PMC_P16_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_OP_SHIFT)) & RTU_PMC_P16_OP_MASK) 1143 1144 #define RTU_PMC_P16_TRANS_MASK (0x30U) 1145 #define RTU_PMC_P16_TRANS_SHIFT (4U) 1146 #define RTU_PMC_P16_TRANS_WIDTH (2U) 1147 #define RTU_PMC_P16_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_TRANS_SHIFT)) & RTU_PMC_P16_TRANS_MASK) 1148 1149 #define RTU_PMC_P16_DREG_MASK (0x40U) 1150 #define RTU_PMC_P16_DREG_SHIFT (6U) 1151 #define RTU_PMC_P16_DREG_WIDTH (1U) 1152 #define RTU_PMC_P16_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_DREG_SHIFT)) & RTU_PMC_P16_DREG_MASK) 1153 1154 #define RTU_PMC_P16_DPOL_MASK (0x80U) 1155 #define RTU_PMC_P16_DPOL_SHIFT (7U) 1156 #define RTU_PMC_P16_DPOL_WIDTH (1U) 1157 #define RTU_PMC_P16_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_DPOL_SHIFT)) & RTU_PMC_P16_DPOL_MASK) 1158 1159 #define RTU_PMC_P16_UA_MASK (0x100U) 1160 #define RTU_PMC_P16_UA_SHIFT (8U) 1161 #define RTU_PMC_P16_UA_WIDTH (1U) 1162 #define RTU_PMC_P16_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_UA_SHIFT)) & RTU_PMC_P16_UA_MASK) 1163 1164 #define RTU_PMC_P16_AO_MASK (0x200U) 1165 #define RTU_PMC_P16_AO_SHIFT (9U) 1166 #define RTU_PMC_P16_AO_WIDTH (1U) 1167 #define RTU_PMC_P16_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P16_AO_SHIFT)) & RTU_PMC_P16_AO_MASK) 1168 /*! @} */ 1169 1170 /*! @name P17 - Program Register 17 */ 1171 /*! @{ */ 1172 1173 #define RTU_PMC_P17_OP_MASK (0x3U) 1174 #define RTU_PMC_P17_OP_SHIFT (0U) 1175 #define RTU_PMC_P17_OP_WIDTH (2U) 1176 #define RTU_PMC_P17_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_OP_SHIFT)) & RTU_PMC_P17_OP_MASK) 1177 1178 #define RTU_PMC_P17_TRANS_MASK (0x30U) 1179 #define RTU_PMC_P17_TRANS_SHIFT (4U) 1180 #define RTU_PMC_P17_TRANS_WIDTH (2U) 1181 #define RTU_PMC_P17_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_TRANS_SHIFT)) & RTU_PMC_P17_TRANS_MASK) 1182 1183 #define RTU_PMC_P17_DREG_MASK (0x40U) 1184 #define RTU_PMC_P17_DREG_SHIFT (6U) 1185 #define RTU_PMC_P17_DREG_WIDTH (1U) 1186 #define RTU_PMC_P17_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_DREG_SHIFT)) & RTU_PMC_P17_DREG_MASK) 1187 1188 #define RTU_PMC_P17_DPOL_MASK (0x80U) 1189 #define RTU_PMC_P17_DPOL_SHIFT (7U) 1190 #define RTU_PMC_P17_DPOL_WIDTH (1U) 1191 #define RTU_PMC_P17_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_DPOL_SHIFT)) & RTU_PMC_P17_DPOL_MASK) 1192 1193 #define RTU_PMC_P17_UA_MASK (0x100U) 1194 #define RTU_PMC_P17_UA_SHIFT (8U) 1195 #define RTU_PMC_P17_UA_WIDTH (1U) 1196 #define RTU_PMC_P17_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_UA_SHIFT)) & RTU_PMC_P17_UA_MASK) 1197 1198 #define RTU_PMC_P17_AO_MASK (0x200U) 1199 #define RTU_PMC_P17_AO_SHIFT (9U) 1200 #define RTU_PMC_P17_AO_WIDTH (1U) 1201 #define RTU_PMC_P17_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P17_AO_SHIFT)) & RTU_PMC_P17_AO_MASK) 1202 /*! @} */ 1203 1204 /*! @name P18 - Program Register 18 */ 1205 /*! @{ */ 1206 1207 #define RTU_PMC_P18_OP_MASK (0x3U) 1208 #define RTU_PMC_P18_OP_SHIFT (0U) 1209 #define RTU_PMC_P18_OP_WIDTH (2U) 1210 #define RTU_PMC_P18_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_OP_SHIFT)) & RTU_PMC_P18_OP_MASK) 1211 1212 #define RTU_PMC_P18_TRANS_MASK (0x30U) 1213 #define RTU_PMC_P18_TRANS_SHIFT (4U) 1214 #define RTU_PMC_P18_TRANS_WIDTH (2U) 1215 #define RTU_PMC_P18_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_TRANS_SHIFT)) & RTU_PMC_P18_TRANS_MASK) 1216 1217 #define RTU_PMC_P18_DREG_MASK (0x40U) 1218 #define RTU_PMC_P18_DREG_SHIFT (6U) 1219 #define RTU_PMC_P18_DREG_WIDTH (1U) 1220 #define RTU_PMC_P18_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_DREG_SHIFT)) & RTU_PMC_P18_DREG_MASK) 1221 1222 #define RTU_PMC_P18_DPOL_MASK (0x80U) 1223 #define RTU_PMC_P18_DPOL_SHIFT (7U) 1224 #define RTU_PMC_P18_DPOL_WIDTH (1U) 1225 #define RTU_PMC_P18_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_DPOL_SHIFT)) & RTU_PMC_P18_DPOL_MASK) 1226 1227 #define RTU_PMC_P18_UA_MASK (0x100U) 1228 #define RTU_PMC_P18_UA_SHIFT (8U) 1229 #define RTU_PMC_P18_UA_WIDTH (1U) 1230 #define RTU_PMC_P18_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_UA_SHIFT)) & RTU_PMC_P18_UA_MASK) 1231 1232 #define RTU_PMC_P18_AO_MASK (0x200U) 1233 #define RTU_PMC_P18_AO_SHIFT (9U) 1234 #define RTU_PMC_P18_AO_WIDTH (1U) 1235 #define RTU_PMC_P18_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P18_AO_SHIFT)) & RTU_PMC_P18_AO_MASK) 1236 /*! @} */ 1237 1238 /*! @name P19 - Program Register 19 */ 1239 /*! @{ */ 1240 1241 #define RTU_PMC_P19_OP_MASK (0x3U) 1242 #define RTU_PMC_P19_OP_SHIFT (0U) 1243 #define RTU_PMC_P19_OP_WIDTH (2U) 1244 #define RTU_PMC_P19_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_OP_SHIFT)) & RTU_PMC_P19_OP_MASK) 1245 1246 #define RTU_PMC_P19_TRANS_MASK (0x30U) 1247 #define RTU_PMC_P19_TRANS_SHIFT (4U) 1248 #define RTU_PMC_P19_TRANS_WIDTH (2U) 1249 #define RTU_PMC_P19_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_TRANS_SHIFT)) & RTU_PMC_P19_TRANS_MASK) 1250 1251 #define RTU_PMC_P19_DREG_MASK (0x40U) 1252 #define RTU_PMC_P19_DREG_SHIFT (6U) 1253 #define RTU_PMC_P19_DREG_WIDTH (1U) 1254 #define RTU_PMC_P19_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_DREG_SHIFT)) & RTU_PMC_P19_DREG_MASK) 1255 1256 #define RTU_PMC_P19_DPOL_MASK (0x80U) 1257 #define RTU_PMC_P19_DPOL_SHIFT (7U) 1258 #define RTU_PMC_P19_DPOL_WIDTH (1U) 1259 #define RTU_PMC_P19_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_DPOL_SHIFT)) & RTU_PMC_P19_DPOL_MASK) 1260 1261 #define RTU_PMC_P19_UA_MASK (0x100U) 1262 #define RTU_PMC_P19_UA_SHIFT (8U) 1263 #define RTU_PMC_P19_UA_WIDTH (1U) 1264 #define RTU_PMC_P19_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_UA_SHIFT)) & RTU_PMC_P19_UA_MASK) 1265 1266 #define RTU_PMC_P19_AO_MASK (0x200U) 1267 #define RTU_PMC_P19_AO_SHIFT (9U) 1268 #define RTU_PMC_P19_AO_WIDTH (1U) 1269 #define RTU_PMC_P19_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P19_AO_SHIFT)) & RTU_PMC_P19_AO_MASK) 1270 /*! @} */ 1271 1272 /*! @name P20 - Program Register 20 */ 1273 /*! @{ */ 1274 1275 #define RTU_PMC_P20_OP_MASK (0x3U) 1276 #define RTU_PMC_P20_OP_SHIFT (0U) 1277 #define RTU_PMC_P20_OP_WIDTH (2U) 1278 #define RTU_PMC_P20_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_OP_SHIFT)) & RTU_PMC_P20_OP_MASK) 1279 1280 #define RTU_PMC_P20_TRANS_MASK (0x30U) 1281 #define RTU_PMC_P20_TRANS_SHIFT (4U) 1282 #define RTU_PMC_P20_TRANS_WIDTH (2U) 1283 #define RTU_PMC_P20_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_TRANS_SHIFT)) & RTU_PMC_P20_TRANS_MASK) 1284 1285 #define RTU_PMC_P20_DREG_MASK (0x40U) 1286 #define RTU_PMC_P20_DREG_SHIFT (6U) 1287 #define RTU_PMC_P20_DREG_WIDTH (1U) 1288 #define RTU_PMC_P20_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_DREG_SHIFT)) & RTU_PMC_P20_DREG_MASK) 1289 1290 #define RTU_PMC_P20_DPOL_MASK (0x80U) 1291 #define RTU_PMC_P20_DPOL_SHIFT (7U) 1292 #define RTU_PMC_P20_DPOL_WIDTH (1U) 1293 #define RTU_PMC_P20_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_DPOL_SHIFT)) & RTU_PMC_P20_DPOL_MASK) 1294 1295 #define RTU_PMC_P20_UA_MASK (0x100U) 1296 #define RTU_PMC_P20_UA_SHIFT (8U) 1297 #define RTU_PMC_P20_UA_WIDTH (1U) 1298 #define RTU_PMC_P20_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_UA_SHIFT)) & RTU_PMC_P20_UA_MASK) 1299 1300 #define RTU_PMC_P20_AO_MASK (0x200U) 1301 #define RTU_PMC_P20_AO_SHIFT (9U) 1302 #define RTU_PMC_P20_AO_WIDTH (1U) 1303 #define RTU_PMC_P20_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P20_AO_SHIFT)) & RTU_PMC_P20_AO_MASK) 1304 /*! @} */ 1305 1306 /*! @name P21 - Program Register 21 */ 1307 /*! @{ */ 1308 1309 #define RTU_PMC_P21_OP_MASK (0x3U) 1310 #define RTU_PMC_P21_OP_SHIFT (0U) 1311 #define RTU_PMC_P21_OP_WIDTH (2U) 1312 #define RTU_PMC_P21_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_OP_SHIFT)) & RTU_PMC_P21_OP_MASK) 1313 1314 #define RTU_PMC_P21_TRANS_MASK (0x30U) 1315 #define RTU_PMC_P21_TRANS_SHIFT (4U) 1316 #define RTU_PMC_P21_TRANS_WIDTH (2U) 1317 #define RTU_PMC_P21_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_TRANS_SHIFT)) & RTU_PMC_P21_TRANS_MASK) 1318 1319 #define RTU_PMC_P21_DREG_MASK (0x40U) 1320 #define RTU_PMC_P21_DREG_SHIFT (6U) 1321 #define RTU_PMC_P21_DREG_WIDTH (1U) 1322 #define RTU_PMC_P21_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_DREG_SHIFT)) & RTU_PMC_P21_DREG_MASK) 1323 1324 #define RTU_PMC_P21_DPOL_MASK (0x80U) 1325 #define RTU_PMC_P21_DPOL_SHIFT (7U) 1326 #define RTU_PMC_P21_DPOL_WIDTH (1U) 1327 #define RTU_PMC_P21_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_DPOL_SHIFT)) & RTU_PMC_P21_DPOL_MASK) 1328 1329 #define RTU_PMC_P21_UA_MASK (0x100U) 1330 #define RTU_PMC_P21_UA_SHIFT (8U) 1331 #define RTU_PMC_P21_UA_WIDTH (1U) 1332 #define RTU_PMC_P21_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_UA_SHIFT)) & RTU_PMC_P21_UA_MASK) 1333 1334 #define RTU_PMC_P21_AO_MASK (0x200U) 1335 #define RTU_PMC_P21_AO_SHIFT (9U) 1336 #define RTU_PMC_P21_AO_WIDTH (1U) 1337 #define RTU_PMC_P21_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P21_AO_SHIFT)) & RTU_PMC_P21_AO_MASK) 1338 /*! @} */ 1339 1340 /*! @name P22 - Program Register 22 */ 1341 /*! @{ */ 1342 1343 #define RTU_PMC_P22_OP_MASK (0x3U) 1344 #define RTU_PMC_P22_OP_SHIFT (0U) 1345 #define RTU_PMC_P22_OP_WIDTH (2U) 1346 #define RTU_PMC_P22_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_OP_SHIFT)) & RTU_PMC_P22_OP_MASK) 1347 1348 #define RTU_PMC_P22_TRANS_MASK (0x30U) 1349 #define RTU_PMC_P22_TRANS_SHIFT (4U) 1350 #define RTU_PMC_P22_TRANS_WIDTH (2U) 1351 #define RTU_PMC_P22_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_TRANS_SHIFT)) & RTU_PMC_P22_TRANS_MASK) 1352 1353 #define RTU_PMC_P22_DREG_MASK (0x40U) 1354 #define RTU_PMC_P22_DREG_SHIFT (6U) 1355 #define RTU_PMC_P22_DREG_WIDTH (1U) 1356 #define RTU_PMC_P22_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_DREG_SHIFT)) & RTU_PMC_P22_DREG_MASK) 1357 1358 #define RTU_PMC_P22_DPOL_MASK (0x80U) 1359 #define RTU_PMC_P22_DPOL_SHIFT (7U) 1360 #define RTU_PMC_P22_DPOL_WIDTH (1U) 1361 #define RTU_PMC_P22_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_DPOL_SHIFT)) & RTU_PMC_P22_DPOL_MASK) 1362 1363 #define RTU_PMC_P22_UA_MASK (0x100U) 1364 #define RTU_PMC_P22_UA_SHIFT (8U) 1365 #define RTU_PMC_P22_UA_WIDTH (1U) 1366 #define RTU_PMC_P22_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_UA_SHIFT)) & RTU_PMC_P22_UA_MASK) 1367 1368 #define RTU_PMC_P22_AO_MASK (0x200U) 1369 #define RTU_PMC_P22_AO_SHIFT (9U) 1370 #define RTU_PMC_P22_AO_WIDTH (1U) 1371 #define RTU_PMC_P22_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P22_AO_SHIFT)) & RTU_PMC_P22_AO_MASK) 1372 /*! @} */ 1373 1374 /*! @name P23 - Program Register 23 */ 1375 /*! @{ */ 1376 1377 #define RTU_PMC_P23_OP_MASK (0x3U) 1378 #define RTU_PMC_P23_OP_SHIFT (0U) 1379 #define RTU_PMC_P23_OP_WIDTH (2U) 1380 #define RTU_PMC_P23_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_OP_SHIFT)) & RTU_PMC_P23_OP_MASK) 1381 1382 #define RTU_PMC_P23_TRANS_MASK (0x30U) 1383 #define RTU_PMC_P23_TRANS_SHIFT (4U) 1384 #define RTU_PMC_P23_TRANS_WIDTH (2U) 1385 #define RTU_PMC_P23_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_TRANS_SHIFT)) & RTU_PMC_P23_TRANS_MASK) 1386 1387 #define RTU_PMC_P23_DREG_MASK (0x40U) 1388 #define RTU_PMC_P23_DREG_SHIFT (6U) 1389 #define RTU_PMC_P23_DREG_WIDTH (1U) 1390 #define RTU_PMC_P23_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_DREG_SHIFT)) & RTU_PMC_P23_DREG_MASK) 1391 1392 #define RTU_PMC_P23_DPOL_MASK (0x80U) 1393 #define RTU_PMC_P23_DPOL_SHIFT (7U) 1394 #define RTU_PMC_P23_DPOL_WIDTH (1U) 1395 #define RTU_PMC_P23_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_DPOL_SHIFT)) & RTU_PMC_P23_DPOL_MASK) 1396 1397 #define RTU_PMC_P23_UA_MASK (0x100U) 1398 #define RTU_PMC_P23_UA_SHIFT (8U) 1399 #define RTU_PMC_P23_UA_WIDTH (1U) 1400 #define RTU_PMC_P23_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_UA_SHIFT)) & RTU_PMC_P23_UA_MASK) 1401 1402 #define RTU_PMC_P23_AO_MASK (0x200U) 1403 #define RTU_PMC_P23_AO_SHIFT (9U) 1404 #define RTU_PMC_P23_AO_WIDTH (1U) 1405 #define RTU_PMC_P23_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P23_AO_SHIFT)) & RTU_PMC_P23_AO_MASK) 1406 /*! @} */ 1407 1408 /*! @name P24 - Program Register 24 */ 1409 /*! @{ */ 1410 1411 #define RTU_PMC_P24_OP_MASK (0x3U) 1412 #define RTU_PMC_P24_OP_SHIFT (0U) 1413 #define RTU_PMC_P24_OP_WIDTH (2U) 1414 #define RTU_PMC_P24_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_OP_SHIFT)) & RTU_PMC_P24_OP_MASK) 1415 1416 #define RTU_PMC_P24_TRANS_MASK (0x30U) 1417 #define RTU_PMC_P24_TRANS_SHIFT (4U) 1418 #define RTU_PMC_P24_TRANS_WIDTH (2U) 1419 #define RTU_PMC_P24_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_TRANS_SHIFT)) & RTU_PMC_P24_TRANS_MASK) 1420 1421 #define RTU_PMC_P24_DREG_MASK (0x40U) 1422 #define RTU_PMC_P24_DREG_SHIFT (6U) 1423 #define RTU_PMC_P24_DREG_WIDTH (1U) 1424 #define RTU_PMC_P24_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_DREG_SHIFT)) & RTU_PMC_P24_DREG_MASK) 1425 1426 #define RTU_PMC_P24_DPOL_MASK (0x80U) 1427 #define RTU_PMC_P24_DPOL_SHIFT (7U) 1428 #define RTU_PMC_P24_DPOL_WIDTH (1U) 1429 #define RTU_PMC_P24_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_DPOL_SHIFT)) & RTU_PMC_P24_DPOL_MASK) 1430 1431 #define RTU_PMC_P24_UA_MASK (0x100U) 1432 #define RTU_PMC_P24_UA_SHIFT (8U) 1433 #define RTU_PMC_P24_UA_WIDTH (1U) 1434 #define RTU_PMC_P24_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_UA_SHIFT)) & RTU_PMC_P24_UA_MASK) 1435 1436 #define RTU_PMC_P24_AO_MASK (0x200U) 1437 #define RTU_PMC_P24_AO_SHIFT (9U) 1438 #define RTU_PMC_P24_AO_WIDTH (1U) 1439 #define RTU_PMC_P24_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P24_AO_SHIFT)) & RTU_PMC_P24_AO_MASK) 1440 /*! @} */ 1441 1442 /*! @name P25 - Program Register 25 */ 1443 /*! @{ */ 1444 1445 #define RTU_PMC_P25_OP_MASK (0x3U) 1446 #define RTU_PMC_P25_OP_SHIFT (0U) 1447 #define RTU_PMC_P25_OP_WIDTH (2U) 1448 #define RTU_PMC_P25_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_OP_SHIFT)) & RTU_PMC_P25_OP_MASK) 1449 1450 #define RTU_PMC_P25_TRANS_MASK (0x30U) 1451 #define RTU_PMC_P25_TRANS_SHIFT (4U) 1452 #define RTU_PMC_P25_TRANS_WIDTH (2U) 1453 #define RTU_PMC_P25_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_TRANS_SHIFT)) & RTU_PMC_P25_TRANS_MASK) 1454 1455 #define RTU_PMC_P25_DREG_MASK (0x40U) 1456 #define RTU_PMC_P25_DREG_SHIFT (6U) 1457 #define RTU_PMC_P25_DREG_WIDTH (1U) 1458 #define RTU_PMC_P25_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_DREG_SHIFT)) & RTU_PMC_P25_DREG_MASK) 1459 1460 #define RTU_PMC_P25_DPOL_MASK (0x80U) 1461 #define RTU_PMC_P25_DPOL_SHIFT (7U) 1462 #define RTU_PMC_P25_DPOL_WIDTH (1U) 1463 #define RTU_PMC_P25_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_DPOL_SHIFT)) & RTU_PMC_P25_DPOL_MASK) 1464 1465 #define RTU_PMC_P25_UA_MASK (0x100U) 1466 #define RTU_PMC_P25_UA_SHIFT (8U) 1467 #define RTU_PMC_P25_UA_WIDTH (1U) 1468 #define RTU_PMC_P25_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_UA_SHIFT)) & RTU_PMC_P25_UA_MASK) 1469 1470 #define RTU_PMC_P25_AO_MASK (0x200U) 1471 #define RTU_PMC_P25_AO_SHIFT (9U) 1472 #define RTU_PMC_P25_AO_WIDTH (1U) 1473 #define RTU_PMC_P25_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P25_AO_SHIFT)) & RTU_PMC_P25_AO_MASK) 1474 /*! @} */ 1475 1476 /*! @name P26 - Program Register 26 */ 1477 /*! @{ */ 1478 1479 #define RTU_PMC_P26_OP_MASK (0x3U) 1480 #define RTU_PMC_P26_OP_SHIFT (0U) 1481 #define RTU_PMC_P26_OP_WIDTH (2U) 1482 #define RTU_PMC_P26_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_OP_SHIFT)) & RTU_PMC_P26_OP_MASK) 1483 1484 #define RTU_PMC_P26_TRANS_MASK (0x30U) 1485 #define RTU_PMC_P26_TRANS_SHIFT (4U) 1486 #define RTU_PMC_P26_TRANS_WIDTH (2U) 1487 #define RTU_PMC_P26_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_TRANS_SHIFT)) & RTU_PMC_P26_TRANS_MASK) 1488 1489 #define RTU_PMC_P26_DREG_MASK (0x40U) 1490 #define RTU_PMC_P26_DREG_SHIFT (6U) 1491 #define RTU_PMC_P26_DREG_WIDTH (1U) 1492 #define RTU_PMC_P26_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_DREG_SHIFT)) & RTU_PMC_P26_DREG_MASK) 1493 1494 #define RTU_PMC_P26_DPOL_MASK (0x80U) 1495 #define RTU_PMC_P26_DPOL_SHIFT (7U) 1496 #define RTU_PMC_P26_DPOL_WIDTH (1U) 1497 #define RTU_PMC_P26_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_DPOL_SHIFT)) & RTU_PMC_P26_DPOL_MASK) 1498 1499 #define RTU_PMC_P26_UA_MASK (0x100U) 1500 #define RTU_PMC_P26_UA_SHIFT (8U) 1501 #define RTU_PMC_P26_UA_WIDTH (1U) 1502 #define RTU_PMC_P26_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_UA_SHIFT)) & RTU_PMC_P26_UA_MASK) 1503 1504 #define RTU_PMC_P26_AO_MASK (0x200U) 1505 #define RTU_PMC_P26_AO_SHIFT (9U) 1506 #define RTU_PMC_P26_AO_WIDTH (1U) 1507 #define RTU_PMC_P26_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P26_AO_SHIFT)) & RTU_PMC_P26_AO_MASK) 1508 /*! @} */ 1509 1510 /*! @name P27 - Program Register 27 */ 1511 /*! @{ */ 1512 1513 #define RTU_PMC_P27_OP_MASK (0x3U) 1514 #define RTU_PMC_P27_OP_SHIFT (0U) 1515 #define RTU_PMC_P27_OP_WIDTH (2U) 1516 #define RTU_PMC_P27_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_OP_SHIFT)) & RTU_PMC_P27_OP_MASK) 1517 1518 #define RTU_PMC_P27_TRANS_MASK (0x30U) 1519 #define RTU_PMC_P27_TRANS_SHIFT (4U) 1520 #define RTU_PMC_P27_TRANS_WIDTH (2U) 1521 #define RTU_PMC_P27_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_TRANS_SHIFT)) & RTU_PMC_P27_TRANS_MASK) 1522 1523 #define RTU_PMC_P27_DREG_MASK (0x40U) 1524 #define RTU_PMC_P27_DREG_SHIFT (6U) 1525 #define RTU_PMC_P27_DREG_WIDTH (1U) 1526 #define RTU_PMC_P27_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_DREG_SHIFT)) & RTU_PMC_P27_DREG_MASK) 1527 1528 #define RTU_PMC_P27_DPOL_MASK (0x80U) 1529 #define RTU_PMC_P27_DPOL_SHIFT (7U) 1530 #define RTU_PMC_P27_DPOL_WIDTH (1U) 1531 #define RTU_PMC_P27_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_DPOL_SHIFT)) & RTU_PMC_P27_DPOL_MASK) 1532 1533 #define RTU_PMC_P27_UA_MASK (0x100U) 1534 #define RTU_PMC_P27_UA_SHIFT (8U) 1535 #define RTU_PMC_P27_UA_WIDTH (1U) 1536 #define RTU_PMC_P27_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_UA_SHIFT)) & RTU_PMC_P27_UA_MASK) 1537 1538 #define RTU_PMC_P27_AO_MASK (0x200U) 1539 #define RTU_PMC_P27_AO_SHIFT (9U) 1540 #define RTU_PMC_P27_AO_WIDTH (1U) 1541 #define RTU_PMC_P27_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P27_AO_SHIFT)) & RTU_PMC_P27_AO_MASK) 1542 /*! @} */ 1543 1544 /*! @name P28 - Program Register 28 */ 1545 /*! @{ */ 1546 1547 #define RTU_PMC_P28_OP_MASK (0x3U) 1548 #define RTU_PMC_P28_OP_SHIFT (0U) 1549 #define RTU_PMC_P28_OP_WIDTH (2U) 1550 #define RTU_PMC_P28_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_OP_SHIFT)) & RTU_PMC_P28_OP_MASK) 1551 1552 #define RTU_PMC_P28_TRANS_MASK (0x30U) 1553 #define RTU_PMC_P28_TRANS_SHIFT (4U) 1554 #define RTU_PMC_P28_TRANS_WIDTH (2U) 1555 #define RTU_PMC_P28_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_TRANS_SHIFT)) & RTU_PMC_P28_TRANS_MASK) 1556 1557 #define RTU_PMC_P28_DREG_MASK (0x40U) 1558 #define RTU_PMC_P28_DREG_SHIFT (6U) 1559 #define RTU_PMC_P28_DREG_WIDTH (1U) 1560 #define RTU_PMC_P28_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_DREG_SHIFT)) & RTU_PMC_P28_DREG_MASK) 1561 1562 #define RTU_PMC_P28_DPOL_MASK (0x80U) 1563 #define RTU_PMC_P28_DPOL_SHIFT (7U) 1564 #define RTU_PMC_P28_DPOL_WIDTH (1U) 1565 #define RTU_PMC_P28_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_DPOL_SHIFT)) & RTU_PMC_P28_DPOL_MASK) 1566 1567 #define RTU_PMC_P28_UA_MASK (0x100U) 1568 #define RTU_PMC_P28_UA_SHIFT (8U) 1569 #define RTU_PMC_P28_UA_WIDTH (1U) 1570 #define RTU_PMC_P28_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_UA_SHIFT)) & RTU_PMC_P28_UA_MASK) 1571 1572 #define RTU_PMC_P28_AO_MASK (0x200U) 1573 #define RTU_PMC_P28_AO_SHIFT (9U) 1574 #define RTU_PMC_P28_AO_WIDTH (1U) 1575 #define RTU_PMC_P28_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P28_AO_SHIFT)) & RTU_PMC_P28_AO_MASK) 1576 /*! @} */ 1577 1578 /*! @name P29 - Program Register 29 */ 1579 /*! @{ */ 1580 1581 #define RTU_PMC_P29_OP_MASK (0x3U) 1582 #define RTU_PMC_P29_OP_SHIFT (0U) 1583 #define RTU_PMC_P29_OP_WIDTH (2U) 1584 #define RTU_PMC_P29_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_OP_SHIFT)) & RTU_PMC_P29_OP_MASK) 1585 1586 #define RTU_PMC_P29_TRANS_MASK (0x30U) 1587 #define RTU_PMC_P29_TRANS_SHIFT (4U) 1588 #define RTU_PMC_P29_TRANS_WIDTH (2U) 1589 #define RTU_PMC_P29_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_TRANS_SHIFT)) & RTU_PMC_P29_TRANS_MASK) 1590 1591 #define RTU_PMC_P29_DREG_MASK (0x40U) 1592 #define RTU_PMC_P29_DREG_SHIFT (6U) 1593 #define RTU_PMC_P29_DREG_WIDTH (1U) 1594 #define RTU_PMC_P29_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_DREG_SHIFT)) & RTU_PMC_P29_DREG_MASK) 1595 1596 #define RTU_PMC_P29_DPOL_MASK (0x80U) 1597 #define RTU_PMC_P29_DPOL_SHIFT (7U) 1598 #define RTU_PMC_P29_DPOL_WIDTH (1U) 1599 #define RTU_PMC_P29_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_DPOL_SHIFT)) & RTU_PMC_P29_DPOL_MASK) 1600 1601 #define RTU_PMC_P29_UA_MASK (0x100U) 1602 #define RTU_PMC_P29_UA_SHIFT (8U) 1603 #define RTU_PMC_P29_UA_WIDTH (1U) 1604 #define RTU_PMC_P29_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_UA_SHIFT)) & RTU_PMC_P29_UA_MASK) 1605 1606 #define RTU_PMC_P29_AO_MASK (0x200U) 1607 #define RTU_PMC_P29_AO_SHIFT (9U) 1608 #define RTU_PMC_P29_AO_WIDTH (1U) 1609 #define RTU_PMC_P29_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P29_AO_SHIFT)) & RTU_PMC_P29_AO_MASK) 1610 /*! @} */ 1611 1612 /*! @name P30 - Program Register 30 */ 1613 /*! @{ */ 1614 1615 #define RTU_PMC_P30_OP_MASK (0x3U) 1616 #define RTU_PMC_P30_OP_SHIFT (0U) 1617 #define RTU_PMC_P30_OP_WIDTH (2U) 1618 #define RTU_PMC_P30_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_OP_SHIFT)) & RTU_PMC_P30_OP_MASK) 1619 1620 #define RTU_PMC_P30_TRANS_MASK (0x30U) 1621 #define RTU_PMC_P30_TRANS_SHIFT (4U) 1622 #define RTU_PMC_P30_TRANS_WIDTH (2U) 1623 #define RTU_PMC_P30_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_TRANS_SHIFT)) & RTU_PMC_P30_TRANS_MASK) 1624 1625 #define RTU_PMC_P30_DREG_MASK (0x40U) 1626 #define RTU_PMC_P30_DREG_SHIFT (6U) 1627 #define RTU_PMC_P30_DREG_WIDTH (1U) 1628 #define RTU_PMC_P30_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_DREG_SHIFT)) & RTU_PMC_P30_DREG_MASK) 1629 1630 #define RTU_PMC_P30_DPOL_MASK (0x80U) 1631 #define RTU_PMC_P30_DPOL_SHIFT (7U) 1632 #define RTU_PMC_P30_DPOL_WIDTH (1U) 1633 #define RTU_PMC_P30_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_DPOL_SHIFT)) & RTU_PMC_P30_DPOL_MASK) 1634 1635 #define RTU_PMC_P30_UA_MASK (0x100U) 1636 #define RTU_PMC_P30_UA_SHIFT (8U) 1637 #define RTU_PMC_P30_UA_WIDTH (1U) 1638 #define RTU_PMC_P30_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_UA_SHIFT)) & RTU_PMC_P30_UA_MASK) 1639 1640 #define RTU_PMC_P30_AO_MASK (0x200U) 1641 #define RTU_PMC_P30_AO_SHIFT (9U) 1642 #define RTU_PMC_P30_AO_WIDTH (1U) 1643 #define RTU_PMC_P30_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P30_AO_SHIFT)) & RTU_PMC_P30_AO_MASK) 1644 /*! @} */ 1645 1646 /*! @name P31 - Program Register 31 */ 1647 /*! @{ */ 1648 1649 #define RTU_PMC_P31_OP_MASK (0x3U) 1650 #define RTU_PMC_P31_OP_SHIFT (0U) 1651 #define RTU_PMC_P31_OP_WIDTH (2U) 1652 #define RTU_PMC_P31_OP(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_OP_SHIFT)) & RTU_PMC_P31_OP_MASK) 1653 1654 #define RTU_PMC_P31_TRANS_MASK (0x30U) 1655 #define RTU_PMC_P31_TRANS_SHIFT (4U) 1656 #define RTU_PMC_P31_TRANS_WIDTH (2U) 1657 #define RTU_PMC_P31_TRANS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_TRANS_SHIFT)) & RTU_PMC_P31_TRANS_MASK) 1658 1659 #define RTU_PMC_P31_DREG_MASK (0x40U) 1660 #define RTU_PMC_P31_DREG_SHIFT (6U) 1661 #define RTU_PMC_P31_DREG_WIDTH (1U) 1662 #define RTU_PMC_P31_DREG(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_DREG_SHIFT)) & RTU_PMC_P31_DREG_MASK) 1663 1664 #define RTU_PMC_P31_DPOL_MASK (0x80U) 1665 #define RTU_PMC_P31_DPOL_SHIFT (7U) 1666 #define RTU_PMC_P31_DPOL_WIDTH (1U) 1667 #define RTU_PMC_P31_DPOL(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_DPOL_SHIFT)) & RTU_PMC_P31_DPOL_MASK) 1668 1669 #define RTU_PMC_P31_UA_MASK (0x100U) 1670 #define RTU_PMC_P31_UA_SHIFT (8U) 1671 #define RTU_PMC_P31_UA_WIDTH (1U) 1672 #define RTU_PMC_P31_UA(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_UA_SHIFT)) & RTU_PMC_P31_UA_MASK) 1673 1674 #define RTU_PMC_P31_AO_MASK (0x200U) 1675 #define RTU_PMC_P31_AO_SHIFT (9U) 1676 #define RTU_PMC_P31_AO_WIDTH (1U) 1677 #define RTU_PMC_P31_AO(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_P31_AO_SHIFT)) & RTU_PMC_P31_AO_MASK) 1678 /*! @} */ 1679 1680 /*! @name ITCTRL - Integration Mode Control Register */ 1681 /*! @{ */ 1682 1683 #define RTU_PMC_ITCTRL_IME_MASK (0x1U) 1684 #define RTU_PMC_ITCTRL_IME_SHIFT (0U) 1685 #define RTU_PMC_ITCTRL_IME_WIDTH (1U) 1686 #define RTU_PMC_ITCTRL_IME(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_ITCTRL_IME_SHIFT)) & RTU_PMC_ITCTRL_IME_MASK) 1687 /*! @} */ 1688 1689 /*! @name CLAIMSET - Claim Tag Set Register */ 1690 /*! @{ */ 1691 1692 #define RTU_PMC_CLAIMSET_SET_MASK (0xFU) 1693 #define RTU_PMC_CLAIMSET_SET_SHIFT (0U) 1694 #define RTU_PMC_CLAIMSET_SET_WIDTH (4U) 1695 #define RTU_PMC_CLAIMSET_SET(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CLAIMSET_SET_SHIFT)) & RTU_PMC_CLAIMSET_SET_MASK) 1696 /*! @} */ 1697 1698 /*! @name CLAIMCLR - Claim Tag Clear Register */ 1699 /*! @{ */ 1700 1701 #define RTU_PMC_CLAIMCLR_CLR_MASK (0xFU) 1702 #define RTU_PMC_CLAIMCLR_CLR_SHIFT (0U) 1703 #define RTU_PMC_CLAIMCLR_CLR_WIDTH (4U) 1704 #define RTU_PMC_CLAIMCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CLAIMCLR_CLR_SHIFT)) & RTU_PMC_CLAIMCLR_CLR_MASK) 1705 /*! @} */ 1706 1707 /*! @name DEVAFF0 - Device Affinity 0 Register */ 1708 /*! @{ */ 1709 1710 #define RTU_PMC_DEVAFF0_Aff0_MASK (0xFFU) 1711 #define RTU_PMC_DEVAFF0_Aff0_SHIFT (0U) 1712 #define RTU_PMC_DEVAFF0_Aff0_WIDTH (8U) 1713 #define RTU_PMC_DEVAFF0_Aff0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_Aff0_SHIFT)) & RTU_PMC_DEVAFF0_Aff0_MASK) 1714 1715 #define RTU_PMC_DEVAFF0_Aff1_MASK (0xFF00U) 1716 #define RTU_PMC_DEVAFF0_Aff1_SHIFT (8U) 1717 #define RTU_PMC_DEVAFF0_Aff1_WIDTH (8U) 1718 #define RTU_PMC_DEVAFF0_Aff1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_Aff1_SHIFT)) & RTU_PMC_DEVAFF0_Aff1_MASK) 1719 1720 #define RTU_PMC_DEVAFF0_Aff2_MASK (0xFF0000U) 1721 #define RTU_PMC_DEVAFF0_Aff2_SHIFT (16U) 1722 #define RTU_PMC_DEVAFF0_Aff2_WIDTH (8U) 1723 #define RTU_PMC_DEVAFF0_Aff2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_Aff2_SHIFT)) & RTU_PMC_DEVAFF0_Aff2_MASK) 1724 1725 #define RTU_PMC_DEVAFF0_MT_MASK (0x1000000U) 1726 #define RTU_PMC_DEVAFF0_MT_SHIFT (24U) 1727 #define RTU_PMC_DEVAFF0_MT_WIDTH (1U) 1728 #define RTU_PMC_DEVAFF0_MT(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_MT_SHIFT)) & RTU_PMC_DEVAFF0_MT_MASK) 1729 1730 #define RTU_PMC_DEVAFF0_U_MASK (0x40000000U) 1731 #define RTU_PMC_DEVAFF0_U_SHIFT (30U) 1732 #define RTU_PMC_DEVAFF0_U_WIDTH (1U) 1733 #define RTU_PMC_DEVAFF0_U(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_U_SHIFT)) & RTU_PMC_DEVAFF0_U_MASK) 1734 1735 #define RTU_PMC_DEVAFF0_M_MASK (0x80000000U) 1736 #define RTU_PMC_DEVAFF0_M_SHIFT (31U) 1737 #define RTU_PMC_DEVAFF0_M_WIDTH (1U) 1738 #define RTU_PMC_DEVAFF0_M(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF0_M_SHIFT)) & RTU_PMC_DEVAFF0_M_MASK) 1739 /*! @} */ 1740 1741 /*! @name DEVAFF1 - Device Affinity 1 Register */ 1742 /*! @{ */ 1743 1744 #define RTU_PMC_DEVAFF1_DEVAFF1_MASK (0xFFFFFFFFU) 1745 #define RTU_PMC_DEVAFF1_DEVAFF1_SHIFT (0U) 1746 #define RTU_PMC_DEVAFF1_DEVAFF1_WIDTH (32U) 1747 #define RTU_PMC_DEVAFF1_DEVAFF1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVAFF1_DEVAFF1_SHIFT)) & RTU_PMC_DEVAFF1_DEVAFF1_MASK) 1748 /*! @} */ 1749 1750 /*! @name DEVARCH - Device Architecture Register */ 1751 /*! @{ */ 1752 1753 #define RTU_PMC_DEVARCH_ARCHID_MASK (0xFFFFU) 1754 #define RTU_PMC_DEVARCH_ARCHID_SHIFT (0U) 1755 #define RTU_PMC_DEVARCH_ARCHID_WIDTH (16U) 1756 #define RTU_PMC_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVARCH_ARCHID_SHIFT)) & RTU_PMC_DEVARCH_ARCHID_MASK) 1757 1758 #define RTU_PMC_DEVARCH_REVISION_MASK (0xF0000U) 1759 #define RTU_PMC_DEVARCH_REVISION_SHIFT (16U) 1760 #define RTU_PMC_DEVARCH_REVISION_WIDTH (4U) 1761 #define RTU_PMC_DEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVARCH_REVISION_SHIFT)) & RTU_PMC_DEVARCH_REVISION_MASK) 1762 1763 #define RTU_PMC_DEVARCH_PRESENT_MASK (0x100000U) 1764 #define RTU_PMC_DEVARCH_PRESENT_SHIFT (20U) 1765 #define RTU_PMC_DEVARCH_PRESENT_WIDTH (1U) 1766 #define RTU_PMC_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVARCH_PRESENT_SHIFT)) & RTU_PMC_DEVARCH_PRESENT_MASK) 1767 1768 #define RTU_PMC_DEVARCH_ARCHITECT_MASK (0xFFE00000U) 1769 #define RTU_PMC_DEVARCH_ARCHITECT_SHIFT (21U) 1770 #define RTU_PMC_DEVARCH_ARCHITECT_WIDTH (11U) 1771 #define RTU_PMC_DEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVARCH_ARCHITECT_SHIFT)) & RTU_PMC_DEVARCH_ARCHITECT_MASK) 1772 /*! @} */ 1773 1774 /*! @name DEVTYPE - Device Type Identifier Register */ 1775 /*! @{ */ 1776 1777 #define RTU_PMC_DEVTYPE_MAJOR_MASK (0xFU) 1778 #define RTU_PMC_DEVTYPE_MAJOR_SHIFT (0U) 1779 #define RTU_PMC_DEVTYPE_MAJOR_WIDTH (4U) 1780 #define RTU_PMC_DEVTYPE_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVTYPE_MAJOR_SHIFT)) & RTU_PMC_DEVTYPE_MAJOR_MASK) 1781 1782 #define RTU_PMC_DEVTYPE_SUB_MASK (0xF0U) 1783 #define RTU_PMC_DEVTYPE_SUB_SHIFT (4U) 1784 #define RTU_PMC_DEVTYPE_SUB_WIDTH (4U) 1785 #define RTU_PMC_DEVTYPE_SUB(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_DEVTYPE_SUB_SHIFT)) & RTU_PMC_DEVTYPE_SUB_MASK) 1786 /*! @} */ 1787 1788 /*! @name PIDR4 - Peripheral Identification Register 4 */ 1789 /*! @{ */ 1790 1791 #define RTU_PMC_PIDR4_DES_2_MASK (0xFU) 1792 #define RTU_PMC_PIDR4_DES_2_SHIFT (0U) 1793 #define RTU_PMC_PIDR4_DES_2_WIDTH (4U) 1794 #define RTU_PMC_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR4_DES_2_SHIFT)) & RTU_PMC_PIDR4_DES_2_MASK) 1795 1796 #define RTU_PMC_PIDR4_SIZE_MASK (0xF0U) 1797 #define RTU_PMC_PIDR4_SIZE_SHIFT (4U) 1798 #define RTU_PMC_PIDR4_SIZE_WIDTH (4U) 1799 #define RTU_PMC_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR4_SIZE_SHIFT)) & RTU_PMC_PIDR4_SIZE_MASK) 1800 /*! @} */ 1801 1802 /*! @name PIDR0 - Peripheral Identification Register 0 */ 1803 /*! @{ */ 1804 1805 #define RTU_PMC_PIDR0_PART_0_MASK (0xFFU) 1806 #define RTU_PMC_PIDR0_PART_0_SHIFT (0U) 1807 #define RTU_PMC_PIDR0_PART_0_WIDTH (8U) 1808 #define RTU_PMC_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR0_PART_0_SHIFT)) & RTU_PMC_PIDR0_PART_0_MASK) 1809 /*! @} */ 1810 1811 /*! @name PIDR1 - Peripheral Identification Register 1 */ 1812 /*! @{ */ 1813 1814 #define RTU_PMC_PIDR1_PART_1_MASK (0xFU) 1815 #define RTU_PMC_PIDR1_PART_1_SHIFT (0U) 1816 #define RTU_PMC_PIDR1_PART_1_WIDTH (4U) 1817 #define RTU_PMC_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR1_PART_1_SHIFT)) & RTU_PMC_PIDR1_PART_1_MASK) 1818 1819 #define RTU_PMC_PIDR1_DES_0_MASK (0xF0U) 1820 #define RTU_PMC_PIDR1_DES_0_SHIFT (4U) 1821 #define RTU_PMC_PIDR1_DES_0_WIDTH (4U) 1822 #define RTU_PMC_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR1_DES_0_SHIFT)) & RTU_PMC_PIDR1_DES_0_MASK) 1823 /*! @} */ 1824 1825 /*! @name PIDR2 - Peripheral Identification Register 2 */ 1826 /*! @{ */ 1827 1828 #define RTU_PMC_PIDR2_DES_1_MASK (0x7U) 1829 #define RTU_PMC_PIDR2_DES_1_SHIFT (0U) 1830 #define RTU_PMC_PIDR2_DES_1_WIDTH (3U) 1831 #define RTU_PMC_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR2_DES_1_SHIFT)) & RTU_PMC_PIDR2_DES_1_MASK) 1832 1833 #define RTU_PMC_PIDR2_JEDEC_MASK (0x8U) 1834 #define RTU_PMC_PIDR2_JEDEC_SHIFT (3U) 1835 #define RTU_PMC_PIDR2_JEDEC_WIDTH (1U) 1836 #define RTU_PMC_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR2_JEDEC_SHIFT)) & RTU_PMC_PIDR2_JEDEC_MASK) 1837 1838 #define RTU_PMC_PIDR2_REVISION_MASK (0xF0U) 1839 #define RTU_PMC_PIDR2_REVISION_SHIFT (4U) 1840 #define RTU_PMC_PIDR2_REVISION_WIDTH (4U) 1841 #define RTU_PMC_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR2_REVISION_SHIFT)) & RTU_PMC_PIDR2_REVISION_MASK) 1842 /*! @} */ 1843 1844 /*! @name PIDR3 - Peripheral Identification Register 3 */ 1845 /*! @{ */ 1846 1847 #define RTU_PMC_PIDR3_CMOD_MASK (0xFU) 1848 #define RTU_PMC_PIDR3_CMOD_SHIFT (0U) 1849 #define RTU_PMC_PIDR3_CMOD_WIDTH (4U) 1850 #define RTU_PMC_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR3_CMOD_SHIFT)) & RTU_PMC_PIDR3_CMOD_MASK) 1851 1852 #define RTU_PMC_PIDR3_REVAND_MASK (0xF0U) 1853 #define RTU_PMC_PIDR3_REVAND_SHIFT (4U) 1854 #define RTU_PMC_PIDR3_REVAND_WIDTH (4U) 1855 #define RTU_PMC_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_PIDR3_REVAND_SHIFT)) & RTU_PMC_PIDR3_REVAND_MASK) 1856 /*! @} */ 1857 1858 /*! @name CIDR0 - Component Identification Register 0 */ 1859 /*! @{ */ 1860 1861 #define RTU_PMC_CIDR0_PRMBL_0_MASK (0xFFU) 1862 #define RTU_PMC_CIDR0_PRMBL_0_SHIFT (0U) 1863 #define RTU_PMC_CIDR0_PRMBL_0_WIDTH (8U) 1864 #define RTU_PMC_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CIDR0_PRMBL_0_SHIFT)) & RTU_PMC_CIDR0_PRMBL_0_MASK) 1865 /*! @} */ 1866 1867 /*! @name CIDR1 - Component Identification Register 1 */ 1868 /*! @{ */ 1869 1870 #define RTU_PMC_CIDR1_PRMBL_1_MASK (0xFU) 1871 #define RTU_PMC_CIDR1_PRMBL_1_SHIFT (0U) 1872 #define RTU_PMC_CIDR1_PRMBL_1_WIDTH (4U) 1873 #define RTU_PMC_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CIDR1_PRMBL_1_SHIFT)) & RTU_PMC_CIDR1_PRMBL_1_MASK) 1874 1875 #define RTU_PMC_CIDR1_CLASS_MASK (0xF0U) 1876 #define RTU_PMC_CIDR1_CLASS_SHIFT (4U) 1877 #define RTU_PMC_CIDR1_CLASS_WIDTH (4U) 1878 #define RTU_PMC_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CIDR1_CLASS_SHIFT)) & RTU_PMC_CIDR1_CLASS_MASK) 1879 /*! @} */ 1880 1881 /*! @name CIDR2 - Component Identification Register 2 */ 1882 /*! @{ */ 1883 1884 #define RTU_PMC_CIDR2_PRMBL_2_MASK (0xFFU) 1885 #define RTU_PMC_CIDR2_PRMBL_2_SHIFT (0U) 1886 #define RTU_PMC_CIDR2_PRMBL_2_WIDTH (8U) 1887 #define RTU_PMC_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CIDR2_PRMBL_2_SHIFT)) & RTU_PMC_CIDR2_PRMBL_2_MASK) 1888 /*! @} */ 1889 1890 /*! @name CIDR3 - Component Identification Register 3 */ 1891 /*! @{ */ 1892 1893 #define RTU_PMC_CIDR3_PRMBL_3_MASK (0xFFU) 1894 #define RTU_PMC_CIDR3_PRMBL_3_SHIFT (0U) 1895 #define RTU_PMC_CIDR3_PRMBL_3_WIDTH (8U) 1896 #define RTU_PMC_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << RTU_PMC_CIDR3_PRMBL_3_SHIFT)) & RTU_PMC_CIDR3_PRMBL_3_MASK) 1897 /*! @} */ 1898 1899 /*! 1900 * @} 1901 */ /* end of group RTU_PMC_Register_Masks */ 1902 1903 /*! 1904 * @} 1905 */ /* end of group RTU_PMC_Peripheral_Access_Layer */ 1906 1907 #endif /* #if !defined(S32Z2_RTU_PMC_H_) */ 1908
