1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RTUE_NIC_D.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_RTUE_NIC_D 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RTUE_NIC_D_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RTUE_NIC_D_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTUE_NIC_D Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTUE_NIC_D_Peripheral_Access_Layer RTUE_NIC_D Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTUE_NIC_D - Register Layout Typedef */ 72 typedef struct { 73 __O uint32_t REMAP; /**< Remap, offset: 0x0 */ 74 } RTUE_NIC_D_Type, *RTUE_NIC_D_MemMapPtr; 75 76 /** Number of instances of the RTUE_NIC_D module. */ 77 #define RTUE_NIC_D_INSTANCE_COUNT (2u) 78 79 /* RTUE_NIC_D - Peripheral instance base addresses */ 80 /** Peripheral RTU0__RTUE_NIC_D base address */ 81 #define IP_RTU0__RTUE_NIC_D_BASE (0x75300000u) 82 /** Peripheral RTU0__RTUE_NIC_D base pointer */ 83 #define IP_RTU0__RTUE_NIC_D ((RTUE_NIC_D_Type *)IP_RTU0__RTUE_NIC_D_BASE) 84 /** Peripheral RTU1__RTUE_NIC_D base address */ 85 #define IP_RTU1__RTUE_NIC_D_BASE (0x75700000u) 86 /** Peripheral RTU1__RTUE_NIC_D base pointer */ 87 #define IP_RTU1__RTUE_NIC_D ((RTUE_NIC_D_Type *)IP_RTU1__RTUE_NIC_D_BASE) 88 /** Array initializer of RTUE_NIC_D peripheral base addresses */ 89 #define IP_RTUE_NIC_D_BASE_ADDRS { IP_RTU0__RTUE_NIC_D_BASE, IP_RTU1__RTUE_NIC_D_BASE } 90 /** Array initializer of RTUE_NIC_D peripheral base pointers */ 91 #define IP_RTUE_NIC_D_BASE_PTRS { IP_RTU0__RTUE_NIC_D, IP_RTU1__RTUE_NIC_D } 92 93 /* ---------------------------------------------------------------------------- 94 -- RTUE_NIC_D Register Masks 95 ---------------------------------------------------------------------------- */ 96 97 /*! 98 * @addtogroup RTUE_NIC_D_Register_Masks RTUE_NIC_D Register Masks 99 * @{ 100 */ 101 102 /*! @name REMAP - Remap */ 103 /*! @{ */ 104 105 #define RTUE_NIC_D_REMAP_remap_MASK (0x3U) 106 #define RTUE_NIC_D_REMAP_remap_SHIFT (0U) 107 #define RTUE_NIC_D_REMAP_remap_WIDTH (2U) 108 #define RTUE_NIC_D_REMAP_remap(x) (((uint32_t)(((uint32_t)(x)) << RTUE_NIC_D_REMAP_remap_SHIFT)) & RTUE_NIC_D_REMAP_remap_MASK) 109 /*! @} */ 110 111 /*! 112 * @} 113 */ /* end of group RTUE_NIC_D_Register_Masks */ 114 115 /*! 116 * @} 117 */ /* end of group RTUE_NIC_D_Peripheral_Access_Layer */ 118 119 #endif /* #if !defined(S32Z2_RTUE_NIC_D_H_) */ 120
