| /hal_nxp-latest/imx/drivers/ |
| D | rdc_semaphore.c | 163 assert ((semaphore->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); in RDC_SEMAPHORE_Reset()
179 assert ((base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); in RDC_SEMAPHORE_ResetAll()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sema42/ |
| D | fsl_sema42.c | 206 if (0U != (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK)) in SEMA42_ResetGate()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/rdc_sema42/ |
| D | fsl_rdc_sema42.c | 220 if (0U != (base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)) in RDC_SEMA42_ResetGate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm4.h | 18234 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| D | K32L3A60_cm0plus.h | 18344 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 31675 __IO uint16_t RSTGT_R; /**< Reset Gate Read,offset: 0x40 */ member
31691 #define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 19895 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| D | MIMXRT685S_cm33.h | 29406 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 38861 __IO uint16_t RSTGT_R; /**< Reset Gate Read,offset: 0x40 */ member
38877 #define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 30169 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 30170 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 29406 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 32555 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| D | MIMXRT595S_cm33.h | 42196 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 40569 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/ |
| D | MCXW716A.h | 31406 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 44112 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 44110 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 44110 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/ |
| D | MIMXRT735S_hifi1.h | 46541 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| D | MIMXRT735S_cm33_core1.h | 46601 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 44112 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 42195 __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 44112 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 44110 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ member
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