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Searched refs:RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h41191 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
41197 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT735S_cm33_core1.h41251 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
41257 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT735S_ezhv.h59540 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
59546 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h44474 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
44480 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT758S_hifi1.h44412 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
44418 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT758S_ezhv.h62685 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
62691 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h44412 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
44418 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT798S_cm33_core1.h44474 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
44480 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)
DMIMXRT798S_ezhv.h62709 #define RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK (0x2000000U) macro
62715 …2_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_SEMA42_3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_SEMA42_3_MASK)