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Searched refs:RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h41039 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
41045 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT735S_cm33_core1.h41099 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
41105 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT735S_ezhv.h59388 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
59394 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h44322 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
44328 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT758S_hifi1.h44260 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
44266 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT758S_ezhv.h62533 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
62539 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h44260 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
44266 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT798S_cm33_core1.h44322 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
44328 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)
DMIMXRT798S_ezhv.h62557 #define RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK (0x10U) macro
62563 …(uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_EDMA2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_EDMA2_MASK)