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Searched refs:RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h62030 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
62036 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
DMIMXRT798S_cm33_core0.h62115 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
62121 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
DMIMXRT798S_ezhv.h61920 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
61926 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h58751 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
58757 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
DMIMXRT735S_cm33_core0.h58890 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
58896 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h62115 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
62121 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)
DMIMXRT758S_ezhv.h61896 #define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK (0x10000U) macro
61902 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)