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Searched refs:RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h18597 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
18603 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
DMIMXRT685S_cm33.h26413 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
26419 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h26413 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
26419 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h31068 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
31074 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
DMIMXRT595S_cm33.h38353 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
38359 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h36726 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
36732 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h38352 #define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U) macro
38358 …(((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)