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Searched refs:ROM (Results 1 – 25 of 92) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/gcc/
DMIMX8UD7xxxxx_cm33_ram.ld32 /* Memory region from [0x0FFC0000-0x0FFC1FFF] is reserved for ROM header */
34 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
DMIMX8UD7xxxxx_cm33_flash.ld45 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/gcc/
DMIMX8UD5xxxxx_cm33_ram.ld32 /* Memory region from [0x0FFC0000-0x0FFC1FFF] is reserved for ROM header */
34 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
DMIMX8UD5xxxxx_cm33_flash.ld45 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/gcc/
DMIMX8US5xxxxx_cm33_ram.ld32 /* Memory region from [0x0FFC0000-0x0FFC1FFF] is reserved for ROM header */
34 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
DMIMX8US5xxxxx_cm33_flash.ld45 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/gcc/
DMIMX8US3xxxxx_cm33_ram.ld32 /* Memory region from [0x0FFC0000-0x0FFC1FFF] is reserved for ROM header */
34 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
DMIMX8US3xxxxx_cm33_flash.ld45 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/gcc/
DMIMX8UD3xxxxx_cm33_ram.ld32 /* Memory region from [0x0FFC0000-0x0FFC1FFF] is reserved for ROM header */
34 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
DMIMX8UD3xxxxx_cm33_flash.ld45 /* Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot */
/hal_nxp-latest/mcux/mcux-sdk/tools/imgutil/
Dreadme.txt12 …information to ROM how to configure the flash on board. For more information, see "QuadSPI serial …
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Devkmimxrt1170_connect_cm4_cm4side.jlinkscript16 // Prepare spin code provided by ROM
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Devkbmimxrt1170_connect_cm4_cm4side.jlinkscript16 // Prepare spin code provided by ROM
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/gcc/
DMCIMX7U3xxxxx_cm4_flash.ld33 /* Memory region from [0x04000000-0x04001FFF] is reserved for ROM header */
DMCIMX7U3xxxxx_cm4_ram.ld33 /* Memory region from [0x1FFD0000-0x1FFD1FFF] is reserved for ROM header */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/gcc/
DMIMXRT595Sxxxx_cm33_ram_ns.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/gcc/
DMIMXRT555Sxxxx_ram.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/gcc/
DMIMXRT533Sxxxx_ram.ld35 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/gcc/
DMCIMX7U5xxxxx_cm4_flash.ld34 /* Memory region from [0x04000000-0x04001FFF] is reserved for ROM header */
DMCIMX7U5xxxxx_cm4_ram.ld34 /* Memory region from [0x1FFD0000-0x1FFD1FFF] is reserved for ROM header */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/gcc/
DMIMXRT685Sxxxx_cm33_ram.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
DMIMXRT685Sxxxx_cm33_ram_ns.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/gcc/
DMIMXRT633Sxxxx_ram.ld36 /* The SRAM region [0x10000-0x1BFFF] is reserved for ROM code. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/gcc/
DMIMX9352_cm33_flash.ld33 /* Memory region from [0x80000000-0x80001FFF] is reserved for ROM header */
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h6280 #define ROM ((ROM_Type *)ROM_BASE) macro
6281 #define ROM_BASE_PTR (ROM)
6285 #define ROM_BASE_PTRS { ROM }
6299 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
6300 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
6301 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
6302 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
6303 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
6304 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
6305 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
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