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Searched refs:RESC_GROUP_SRAMS_START (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.c199 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM0_MASK},
200 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM1_MASK},
201 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM2_MASK},
202 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM3_MASK},
203 [kResc_SRAM4_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM4_MASK},
204 [kResc_SRAM5_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM5_MASK},
205 [kResc_SRAM6_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM6_MASK},
206 [kResc_SRAM7_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM7_MASK},
207 [kResc_SRAM8_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM8_MASK},
208 [kResc_SRAM9_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM9_MASK},
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Dfsl_pm_device.h167 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
169 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.c199 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM0_MASK},
200 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM1_MASK},
201 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM2_MASK},
202 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM3_MASK},
203 [kResc_SRAM4_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM4_MASK},
204 [kResc_SRAM5_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM5_MASK},
205 [kResc_SRAM6_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM6_MASK},
206 [kResc_SRAM7_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM7_MASK},
207 [kResc_SRAM8_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM8_MASK},
208 [kResc_SRAM9_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM9_MASK},
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Dfsl_pm_device.h167 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
169 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.c199 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM0_MASK},
200 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM1_MASK},
201 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM2_MASK},
202 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM3_MASK},
203 [kResc_SRAM4_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM4_MASK},
204 [kResc_SRAM5_64KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM5_MASK},
205 [kResc_SRAM6_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM6_MASK},
206 [kResc_SRAM7_128KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM7_MASK},
207 [kResc_SRAM8_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM8_MASK},
208 [kResc_SRAM9_256KB - RESC_GROUP_SRAMS_START] = {3U, PMC_PDSLEEPCFG2_SRAM9_MASK},
[all …]
Dfsl_pm_device.h167 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
169 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT533S/
Dfsl_pm_device.c172 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK,
173 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK,
174 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK,
175 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK,
176 [kResc_SRAM4_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK,
177 [kResc_SRAM5_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK,
178 [kResc_SRAM6_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK,
179 [kResc_SRAM7_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK,
180 [kResc_SRAM8_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK,
181 [kResc_SRAM9_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK,
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Dfsl_pm_device.h134 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
136 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT555S/
Dfsl_pm_device.c172 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK,
173 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK,
174 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK,
175 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK,
176 [kResc_SRAM4_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK,
177 [kResc_SRAM5_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK,
178 [kResc_SRAM6_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK,
179 [kResc_SRAM7_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK,
180 [kResc_SRAM8_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK,
181 [kResc_SRAM9_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK,
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Dfsl_pm_device.h134 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
136 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT595S/
Dfsl_pm_device.c172 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK,
173 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK,
174 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK,
175 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK,
176 [kResc_SRAM4_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK,
177 [kResc_SRAM5_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK,
178 [kResc_SRAM6_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK,
179 [kResc_SRAM7_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK,
180 [kResc_SRAM8_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK,
181 [kResc_SRAM9_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK,
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Dfsl_pm_device.h134 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
136 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT685S/
Dfsl_pm_device.c180 [kResc_SRAM0_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK,
181 [kResc_SRAM1_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK,
182 [kResc_SRAM2_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK,
183 [kResc_SRAM3_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK,
184 [kResc_SRAM4_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK,
185 [kResc_SRAM5_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK,
186 [kResc_SRAM6_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK,
187 [kResc_SRAM7_32KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK,
188 [kResc_SRAM8_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK,
189 [kResc_SRAM9_64KB - RESC_GROUP_SRAMS_START] = SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK,
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Dfsl_pm_device.h122 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB macro
124 #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1