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Searched refs:REG_ACCESS (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip_HeaderWrapper_S32XX.h136 #define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)])))) macro
139 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
140 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex))
141 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
142 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex))
143 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex))
144 #define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex))
145 #define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex))
146 #define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELR, (regIndex))
147 #define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex))
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DAdc_Sar_Ip_HeaderWrapper_S32XX_AE.h131 #define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)])))) macro
134 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
135 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex))
136 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
137 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex))
138 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex))
139 #define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex))
140 #define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex))
141 #define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELR, (regIndex))
142 #define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex))
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/hal_nxp-latest/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HeaderWrapper_S32K3.h166 #define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)])))) macro
169 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
170 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex))
171 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
172 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex))
173 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex))
174 #define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex))
175 #define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex))
176 #define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELRPI[0U], (regIndex))
177 #define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex))
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