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Searched refs:REG_2P5 (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/pmu/
Dfsl_pmu.h393 base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; in PMU_2P5EnableWeakRegulator()
397 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; in PMU_2P5EnableWeakRegulator()
417 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); in PMU_2P5SetRegulatorOutputVoltage()
433 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value); in PMU_2P5SetBrownoutOffsetVoltage()
446 base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; in PMU_2P5EnablePullDown()
450 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; in PMU_2P5EnablePullDown()
462 base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; in PMU_2P1EnablePullDown()
466 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; in PMU_2P1EnablePullDown()
480 base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK; in PMU_2P5EnableCurrentLimit()
484 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK; in PMU_2P5EnableCurrentLimit()
[all …]
Dfsl_pmu.c45 if (PMU_REG_2P5_OK_VDD2P5_MASK == (PMU_REG_2P5_OK_VDD2P5_MASK & base->REG_2P5)) in PMU_GetStatusFlags()
49 if (PMU_REG_2P5_BO_VDD2P5_MASK == (PMU_REG_2P5_BO_VDD2P5_MASK & base->REG_2P5)) in PMU_GetStatusFlags()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28579 …__IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 … member
28611 #define PMU_REG_2P5_REG(base) ((base)->REG_2P5)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22450 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h25060 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h29103 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h29124 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h30175 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h31572 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h32882 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33423 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32314 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h34956 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h34949 __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ member