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Searched refs:REGFILE_WAR_WAR5_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h28593 #define REGFILE_WAR_WAR5_MASK (0x20U) macro
28599 … (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR5_SHIFT)) & REGFILE_WAR_WAR5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h30762 #define REGFILE_WAR_WAR5_MASK (0x20U) macro
30768 … (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR5_SHIFT)) & REGFILE_WAR_WAR5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h35719 #define REGFILE_WAR_WAR5_MASK (0x20U) macro
35725 … (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR5_SHIFT)) & REGFILE_WAR_WAR5_MASK)
DMCXW727C_cm33_core1.h40912 #define REGFILE_WAR_WAR5_MASK (0x20U) macro
40918 … (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR5_SHIFT)) & REGFILE_WAR_WAR5_MASK)