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Searched refs:REG1 (Results 1 – 25 of 59) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.h469 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
470 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
515 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
516 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule); in DCDC_SetLPComparatorBiasValue()
Dfsl_dcdc.c482 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
501 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
511 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
818 tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK; in DCDC_SetInternalRegulatorConfig()
821 tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK); in DCDC_SetInternalRegulatorConfig()
829 base->REG1 = tmp32; in DCDC_SetInternalRegulatorConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.h827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; in DCDC_SetLPComparatorBiasValue()
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); in DCDC_SetLPComparatorBiasValue()
Dfsl_dcdc.c361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
380 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_dcdc.c267 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
286 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
Dfsl_dcdc.h651 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
652 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_dcdc.c267 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
286 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
Dfsl_dcdc.h651 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
652 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_dcdc.c267 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
286 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
Dfsl_dcdc.h651 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
652 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_dcdc.c267 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | in DCDC_SetLoopControlConfig()
286 base->REG1 = tmp32; in DCDC_SetLoopControlConfig()
Dfsl_dcdc.h651 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; in DCDC_SetBandgapVoltageTrimValue()
652 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); in DCDC_SetBandgapVoltageTrimValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h1297 __IO uint32_t REG1; /**< DCDC REGISTER 1, offset: 0x4 */ member
1318 #define DCDC_REG1_REG(base) ((base)->REG1)

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