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Searched refs:REG0 (Results 1 – 25 of 73) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
224 base->REG0 = tmp32; in DCDC_SetClockSource()
279 tmp32 = base->REG0 & ~(DCDC_REG0_XTALOK_DISABLE_MASK in DCDC_SetDetectionConfig()
334 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
377 tmp32 = base->REG0 & in DCDC_SetLowPowerConfig()
395 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
408 if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_GetstatusFlags()
427 base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK; in DCDC_ResetCurrentAlertSignal()
431 base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK; in DCDC_ResetCurrentAlertSignal()
598 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_AdjustTargetVoltage()
[all …]
Dfsl_dcdc.h385 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
389 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
236 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
269 base->REG0 = tmp32; in DCDC_SetClockSource()
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); in DCDC_SetLowPowerConfig()
310 base->REG0 = tmp32; in DCDC_SetLowPowerConfig()
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); in DCDC_BootIntoDCM()
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; in DCDC_BootIntoCCM()
Dfsl_dcdc.h571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0StandbyModeTargetVoltage()
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8StandbyModeTargetVoltage()
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P8BuckModeTargetVoltage()
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; in DCDC_EnableOutputRangeComparator()
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_dcdc.c159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
183 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
216 base->REG0 = tmp32; in DCDC_SetClockSource()
Dfsl_dcdc.h362 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
437 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
724 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_dcdc.c159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
183 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
216 base->REG0 = tmp32; in DCDC_SetClockSource()
Dfsl_dcdc.h362 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
437 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
724 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_dcdc.c159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
183 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
216 base->REG0 = tmp32; in DCDC_SetClockSource()
Dfsl_dcdc.h362 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
437 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
724 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_dcdc.c159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
183 base->REG0 = tmp32; in DCDC_SetDetectionConfig()
197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
216 base->REG0 = tmp32; in DCDC_SetClockSource()
Dfsl_dcdc.h362 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
437 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) in DCDC_SetVDD1P0BuckModeTargetVoltage()
724 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); in DCDC_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1010/
Dclock_config.c166 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) in BOARD_BootClockRUN()

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