Home
last modified time | relevance | path

Searched refs:RDC_SEMAPHORE2_BASE (Results 1 – 25 of 39) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h46478 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46480 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46482 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h46476 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46478 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46480 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h46476 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46478 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46480 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h46478 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46480 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46482 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h46478 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46480 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46482 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h46476 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46478 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46480 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
DMIMX8MN6_ca53.h46490 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
46492 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
46494 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h47564 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
47566 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
47568 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h49737 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
49739 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
49741 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h49737 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
49739 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
49741 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h31742 #define RDC_SEMAPHORE2_BASE (0x420F8000u) macro
31744 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
31747 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h49737 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
49739 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
49741 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h49737 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
49739 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
49741 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h38927 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
38929 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
38932 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h64385 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
64387 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
64389 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
DMIMXRT1175_cm7.h63483 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
63485 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
63487 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h62981 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
62983 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
62985 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
DMIMXRT1165_cm4.h63883 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
63885 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
63887 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h63483 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
63485 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
63487 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h64973 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
64975 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
64977 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h69346 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
69348 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
69350 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h64973 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
64975 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
64977 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h64973 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
64975 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
64977 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h64973 #define RDC_SEMAPHORE2_BASE (0x303C0000u) macro
64975 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
64977 #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h69845 #define RDC_SEMAPHORE2_BASE (0x40CCC000u) macro
69847 #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
69849 #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }

12