| /hal_nxp-latest/mcux/mcux-sdk/drivers/esai/ |
| D | fsl_esai.c | 178 base->RCR &= in ESAI_SetCustomerProtocol()
181 base->RCR |= ESAI_RCR_RFSR(protocol->fsEarly) | ESAI_RCR_RFSL(protocol->fsOneBit) | in ESAI_SetCustomerProtocol()
563 base->RCR &= ~(ESAI_RCR_RE0_MASK | ESAI_RCR_RE1_MASK | ESAI_RCR_RE2_MASK | ESAI_RCR_RE3_MASK); in ESAI_RxReset()
564 base->RCR |= ESAI_RCR_RPR_MASK; in ESAI_RxReset()
565 base->RCR &= ~ESAI_RCR_RPR_MASK; in ESAI_RxReset()
613 …val = base->RCR & ~(ESAI_RCR_RE3_MASK | ESAI_RCR_RE2_MASK | ESAI_RCR_RE1_MASK | ESAI_RCR_RE0_MASK); in ESAI_RxEnable()
615 base->RCR = val; in ESAI_RxEnable()
695 base->RCR &= ~ESAI_RCR_RSWS_MASK; in ESAI_RxSetFormat()
696 base->RCR |= ESAI_RCR_RSWS(format->slotType); in ESAI_RxSetFormat()
1232 ((ESAI->RCR & (uint32_t)kESAI_TransmitInterruptEnable) != 0U)) in ESAI_DriverIRQHandler()
[all …]
|
| D | fsl_esai.h | 567 base->RCR |= mask; in ESAI_RxEnableInterrupts()
589 base->RCR &= (~mask); in ESAI_RxDisableInterrupts()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/dac14/ |
| D | fsl_dac14.h | 184 base->RCR |= HPDAC_RCR_SWRST_MASK; in DAC14_DoSoftwareReset()
185 base->RCR &= ~HPDAC_RCR_SWRST_MASK; in DAC14_DoSoftwareReset()
197 base->RCR |= HPDAC_RCR_FIFORST_MASK; in DAC14_DoFIFOReset()
198 base->RCR &= ~HPDAC_RCR_FIFORST_MASK; in DAC14_DoFIFOReset()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/dac_1/ |
| D | fsl_dac.h | 259 base->RCR |= mask; in DAC_SetReset()
273 base->RCR &= ~mask; in DAC_ClearReset()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/mu1/ |
| D | fsl_mu.h | 662 base->RCR |= tmp; in MU_EnableInterrupts()
718 base->RCR &= ~tmp; in MU_DisableInterrupts()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/upower/ |
| D | upower_api.c | 261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
3170 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_rx()
|
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/upower/ |
| D | upower_api.c | 261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
3170 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_rx()
|
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/upower/ |
| D | upower_api.c | 261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
3170 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_rx()
|
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/upower/ |
| D | upower_api.c | 261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
3170 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_rx()
|
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/upower/ |
| D | upower_api.c | 261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
3170 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_rx()
|
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
|
| /hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/enet/ |
| D | fsl_enet_cmsis.c | 159 uint32_t rcr = enet->resource->base->RCR; in ENET_CommonControl()
252 enet->resource->base->RCR = rcr; in ENET_CommonControl()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/ |
| D | fsl_sentinel.c | 28 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
75 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/enet/ |
| D | fsl_enet.c | 632 base->RCR = rcr; in ENET_SetMacController()
1103 uint32_t rcr = base->RCR; in ENET_SetMII()
1146 base->RCR = rcr; in ENET_SetMII()
2358 if (0U != (base->RCR & ENET_RCR_PROM_MASK)) in ENET_GetRxFrame()
|
| D | fsl_enet.h | 126 ((((x)->RCR & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT) - ENET_FRAME_CRC_LEN)
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/ |
| D | fsl_sentinel.c | 41 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/ |
| D | fsl_sentinel.c | 41 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/ |
| D | fsl_sentinel.c | 41 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/ |
| D | fsl_sentinel.c | 41 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/ |
| D | fsl_sentinel.c | 41 SENTINEL__MUA_RTD->RCR = 0U; /* Disable all receive interrupts. */ in SENTINEL_Init()
|
| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_MU.h | 94 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
|
