Searched refs:RAMCR (Results 1 – 5 of 5) sorted by relevance
336 …IP_SMU__SRAMCTL_0->RAMCR |= ((IP_SMU__SRAMCTL_0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_… in Clock_Ip_SRAMControllerSetRamIWS()337 …IP_SMU__SRAMCTL_1->RAMCR |= ((IP_SMU__SRAMCTL_1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_… in Clock_Ip_SRAMControllerSetRamIWS()338 …IP_SMU__SRAMCTL_2->RAMCR |= ((IP_SMU__SRAMCTL_2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_… in Clock_Ip_SRAMControllerSetRamIWS()339 …IP_SMU__SRAMCTL_3->RAMCR |= ((IP_SMU__SRAMCTL_3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_… in Clock_Ip_SRAMControllerSetRamIWS()341 …IP_RTU0__SRAMCTL_C0->RAMCR |= ((IP_RTU0__SRAMCTL_C0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()342 …IP_RTU0__SRAMCTL_C1->RAMCR |= ((IP_RTU0__SRAMCTL_C1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()343 …IP_RTU0__SRAMCTL_C2->RAMCR |= ((IP_RTU0__SRAMCTL_C2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()344 …IP_RTU0__SRAMCTL_C3->RAMCR |= ((IP_RTU0__SRAMCTL_C3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()345 …IP_RTU0__SRAMCTL_C4->RAMCR |= ((IP_RTU0__SRAMCTL_C4->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()346 …IP_RTU0__SRAMCTL_C5->RAMCR |= ((IP_RTU0__SRAMCTL_C5->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RA… in Clock_Ip_SRAMControllerSetRamIWS()[all …]
73 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member
44489 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member
31044 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member45783 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member363049 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member
31034 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member45773 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member362986 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ member
