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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/TransformFunctions/
Darm_cfft_radix2_q15.c98 q31_t T, S, R; in arm_radix2_butterfly_q15() local
125 R = __QSUB16(T, S); in arm_radix2_butterfly_q15()
130 out1 = __SMUAD(coeff, R) >> 16; in arm_radix2_butterfly_q15()
131 out2 = __SMUSDX(coeff, R); in arm_radix2_butterfly_q15()
133 out1 = __SMUSDX(R, coeff) >> 16U; in arm_radix2_butterfly_q15()
134 out2 = __SMUAD(coeff, R); in arm_radix2_butterfly_q15()
155 R = __QSUB16(T, S); in arm_radix2_butterfly_q15()
160 out1 = __SMUAD(coeff, R) >> 16; in arm_radix2_butterfly_q15()
161 out2 = __SMUSDX(coeff, R); in arm_radix2_butterfly_q15()
164 out1 = __SMUSDX(R, coeff) >> 16U; in arm_radix2_butterfly_q15()
[all …]
Darm_cfft_radix4_q15.c156 q31_t R, S, T, U; in arm_radix4_butterfly_q15() local
213 R = __QADD16(T, S); in arm_radix4_butterfly_q15()
235 write_q15x2_ia (&pSi0, __SHADD16(R, T)); in arm_radix4_butterfly_q15()
238 R = __QSUB16(R, T); in arm_radix4_butterfly_q15()
245 out1 = __SMUAD(C2, R) >> 16U; in arm_radix4_butterfly_q15()
247 out2 = __SMUSDX(C2, R); in arm_radix4_butterfly_q15()
250 out1 = __SMUSDX(R, C2) >> 16U; in arm_radix4_butterfly_q15()
252 out2 = __SMUAD(C2, R); in arm_radix4_butterfly_q15()
276 R = __QASX(S, T); in arm_radix4_butterfly_q15()
281 R = __QSAX(S, T); in arm_radix4_butterfly_q15()
[all …]
Darm_cfft_q15.c702 q31_t T, S, R; in arm_cfft_radix4by2_q15() local
726 R = __QSUB16(T, S); in arm_cfft_radix4by2_q15()
731 out1 = __SMUAD(coeff, R) >> 16U; in arm_cfft_radix4by2_q15()
732 out2 = __SMUSDX(coeff, R); in arm_cfft_radix4by2_q15()
734 out1 = __SMUSDX(R, coeff) >> 16U; in arm_cfft_radix4by2_q15()
735 out2 = __SMUAD(coeff, R); in arm_cfft_radix4by2_q15()
801 q31_t T, S, R; in arm_cfft_radix4by2_inverse_q15() local
825 R = __QSUB16(T, S); in arm_cfft_radix4by2_inverse_q15()
830 out1 = __SMUSD(coeff, R) >> 16U; in arm_cfft_radix4by2_inverse_q15()
831 out2 = __SMUADX(coeff, R); in arm_cfft_radix4by2_inverse_q15()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/upower/
Dupmu.h34 vuint32_t R; member
46 vuint32_t R; member
59 vuint32_t R; member
71 vuint32_t R; member
89 vuint32_t R; member
105 vuint32_t R; member
123 vuint32_t R; member
141 vuint32_t R; member
159 vuint32_t R; member
172 vuint32_t R; member
[all …]
Dupower_api.c249 (mu->TSR.R == UPWR_MU_TSR_EMPTY)) { /* ... Tx registers empty: */ in upwr_txrx_isr()
252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
259 if (mu->RSR.R != 0UL) { /* Rx ISR occurred */ in upwr_txrx_isr()
261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
639 while (mu->TSR.R != UPWR_MU_TSR_EMPTY) { /* wait any Tx ... in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
836 txmsg.word2 = config->R; in upwr_xcp_config()
2030 txmsg.word2 = param->R; /* just 1 word, so that's ok */ in upwr_pwm_param()
3062 return (upwr_alarm_t)(3U & (mu->FSR.R >> 1U)); /* FSR[2:1] */ in upwr_alarm_code()
[all …]
Dupower_soc_defs.h263 uint32_t R; member
360 uint32_t R; member
1005 volatile uint32_t R; member
1055 volatile uint32_t R; member
1133 volatile uint32_t R; member
1180 *cfg = mon_cfg.R; in set_mon_cfg()
1218 uint32_t R; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/upower/
Dupmu.h34 vuint32_t R; member
46 vuint32_t R; member
59 vuint32_t R; member
71 vuint32_t R; member
89 vuint32_t R; member
105 vuint32_t R; member
123 vuint32_t R; member
141 vuint32_t R; member
159 vuint32_t R; member
172 vuint32_t R; member
[all …]
Dupower_api.c249 (mu->TSR.R == UPWR_MU_TSR_EMPTY)) { /* ... Tx registers empty: */ in upwr_txrx_isr()
252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
259 if (mu->RSR.R != 0UL) { /* Rx ISR occurred */ in upwr_txrx_isr()
261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
639 while (mu->TSR.R != UPWR_MU_TSR_EMPTY) { /* wait any Tx ... in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
836 txmsg.word2 = config->R; in upwr_xcp_config()
2030 txmsg.word2 = param->R; /* just 1 word, so that's ok */ in upwr_pwm_param()
3062 return (upwr_alarm_t)(3U & (mu->FSR.R >> 1U)); /* FSR[2:1] */ in upwr_alarm_code()
[all …]
Dupower_soc_defs.h263 uint32_t R; member
360 uint32_t R; member
1005 volatile uint32_t R; member
1055 volatile uint32_t R; member
1133 volatile uint32_t R; member
1180 *cfg = mon_cfg.R; in set_mon_cfg()
1218 uint32_t R; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/upower/
Dupmu.h34 vuint32_t R; member
46 vuint32_t R; member
59 vuint32_t R; member
71 vuint32_t R; member
89 vuint32_t R; member
105 vuint32_t R; member
123 vuint32_t R; member
141 vuint32_t R; member
159 vuint32_t R; member
172 vuint32_t R; member
[all …]
Dupower_api.c249 (mu->TSR.R == UPWR_MU_TSR_EMPTY)) { /* ... Tx registers empty: */ in upwr_txrx_isr()
252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
259 if (mu->RSR.R != 0UL) { /* Rx ISR occurred */ in upwr_txrx_isr()
261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
639 while (mu->TSR.R != UPWR_MU_TSR_EMPTY) { /* wait any Tx ... in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
836 txmsg.word2 = config->R; in upwr_xcp_config()
2030 txmsg.word2 = param->R; /* just 1 word, so that's ok */ in upwr_pwm_param()
3062 return (upwr_alarm_t)(3U & (mu->FSR.R >> 1U)); /* FSR[2:1] */ in upwr_alarm_code()
[all …]
Dupower_soc_defs.h263 uint32_t R; member
360 uint32_t R; member
1005 volatile uint32_t R; member
1055 volatile uint32_t R; member
1133 volatile uint32_t R; member
1180 *cfg = mon_cfg.R; in set_mon_cfg()
1218 uint32_t R; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/upower/
Dupmu.h34 vuint32_t R; member
46 vuint32_t R; member
59 vuint32_t R; member
71 vuint32_t R; member
89 vuint32_t R; member
105 vuint32_t R; member
123 vuint32_t R; member
141 vuint32_t R; member
159 vuint32_t R; member
172 vuint32_t R; member
[all …]
Dupower_api.c249 (mu->TSR.R == UPWR_MU_TSR_EMPTY)) { /* ... Tx registers empty: */ in upwr_txrx_isr()
252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
259 if (mu->RSR.R != 0UL) { /* Rx ISR occurred */ in upwr_txrx_isr()
261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
639 while (mu->TSR.R != UPWR_MU_TSR_EMPTY) { /* wait any Tx ... in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
836 txmsg.word2 = config->R; in upwr_xcp_config()
2030 txmsg.word2 = param->R; /* just 1 word, so that's ok */ in upwr_pwm_param()
3062 return (upwr_alarm_t)(3U & (mu->FSR.R >> 1U)); /* FSR[2:1] */ in upwr_alarm_code()
[all …]
Dupower_soc_defs.h263 uint32_t R; member
360 uint32_t R; member
1005 volatile uint32_t R; member
1055 volatile uint32_t R; member
1133 volatile uint32_t R; member
1180 *cfg = mon_cfg.R; in set_mon_cfg()
1218 uint32_t R; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/upower/
Dupmu.h34 vuint32_t R; member
46 vuint32_t R; member
59 vuint32_t R; member
71 vuint32_t R; member
89 vuint32_t R; member
105 vuint32_t R; member
123 vuint32_t R; member
141 vuint32_t R; member
159 vuint32_t R; member
172 vuint32_t R; member
[all …]
Dupower_api.c249 (mu->TSR.R == UPWR_MU_TSR_EMPTY)) { /* ... Tx registers empty: */ in upwr_txrx_isr()
252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
259 if (mu->RSR.R != 0UL) { /* Rx ISR occurred */ in upwr_txrx_isr()
261 mu->RCR.R = 0U; /* disable the interrupt until data is read */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
639 while (mu->TSR.R != UPWR_MU_TSR_EMPTY) { /* wait any Tx ... in upwr_init()
714 mu->RCR.R = 1U; /* enable only RR[0] receive interrupt */ in upwr_init()
836 txmsg.word2 = config->R; in upwr_xcp_config()
2030 txmsg.word2 = param->R; /* just 1 word, so that's ok */ in upwr_pwm_param()
3062 return (upwr_alarm_t)(3U & (mu->FSR.R >> 1U)); /* FSR[2:1] */ in upwr_alarm_code()
[all …]
Dupower_soc_defs.h263 uint32_t R; member
360 uint32_t R; member
1005 volatile uint32_t R; member
1055 volatile uint32_t R; member
1133 volatile uint32_t R; member
1180 *cfg = mon_cfg.R; in set_mon_cfg()
1218 uint32_t R; member
/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm4-cm7/src/
Dmmcau_md5_functions.s9 # DEPARTMENT : MSG R&D Core and Platforms
Dmmcau_sha1_functions.s9 # DEPARTMENT : MSG R&D Core and Platforms
Dmmcau_sha256_functions.s9 # DEPARTMENT : MSG R&D Core and Platforms
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SMU_SEMA42.h79 __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ member
DS32Z2_CE_SEMA42.h79 __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ member
DS32Z2_RTU_SEMA42.h79 __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SEMA42.h79 __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ member

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