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Searched refs:QuadSPI_SR_TXFULL_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h565 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
568 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h588 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
591 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h133 kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h972 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
975 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18858 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
18860 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19831 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
19833 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18390 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
18392 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18388 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
18390 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27706 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
27708 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27707 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
27709 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44391 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
44393 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46564 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
46566 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46564 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
46566 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46564 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
46566 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46564 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) macro
46566 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30673 #define QuadSPI_SR_TXFULL_MASK 0x8000000u macro
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37872 #define QuadSPI_SR_TXFULL_MASK 0x8000000u macro