| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_QUADSPI.h | 535 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
538 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_QUADSPI.h | 558 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
561 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/ |
| D | fsl_qspi.h | 141 kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 952 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
955 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HwAccess.h | 738 RegValue = (RegValue & QuadSPI_SR_RXWE_MASK) >> QuadSPI_SR_RXWE_SHIFT; in Qspi_Ip_GetRxDataEvent()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/ |
| D | Qspi_Ip_HwAccess.h | 1057 RegValue = (RegValue & QuadSPI_SR_RXWE_MASK); in Qspi_Ip_GetRxDataEvent()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/ |
| D | MK80F25615.h | 18840 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
18842 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 19813 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
19815 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/ |
| D | MK28FA15.h | 18372 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
18374 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/ |
| D | MK27FA15.h | 18370 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
18372 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 27679 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
27681 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 27680 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
27682 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 44373 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
44375 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46546 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
46548 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46546 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
46548 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 46546 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
46548 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 46546 #define QuadSPI_SR_RXWE_MASK (0x10000U) macro
46548 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 30665 #define QuadSPI_SR_RXWE_MASK 0x10000u macro
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 37864 #define QuadSPI_SR_RXWE_MASK 0x10000u macro
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