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Searched refs:QuadSPI_SR_RXFULL_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h540 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
543 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h563 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
566 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h140 kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h957 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
960 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18843 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
18845 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19816 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
19818 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18375 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
18377 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18373 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
18375 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27683 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
27685 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27684 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
27686 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44377 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
44379 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46550 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
46552 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46550 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
46552 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46550 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
46552 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46550 #define QuadSPI_SR_RXFULL_MASK (0x80000U) macro
46552 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30667 #define QuadSPI_SR_RXFULL_MASK 0x80000u macro
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37866 #define QuadSPI_SR_RXFULL_MASK 0x80000u macro