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Searched refs:QuadSPI_SR_DLPSMP_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h132 kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18861 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
18863 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19834 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
19836 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18393 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
18395 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18391 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
18393 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27710 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
27712 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27711 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
27713 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44395 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
44397 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46568 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
46570 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46568 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
46570 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30675 #define QuadSPI_SR_DLPSMP_MASK 0xE0000000u macro
30677 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46568 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
46570 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46568 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) macro
46570 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37874 #define QuadSPI_SR_DLPSMP_MASK 0xE0000000u macro
37876 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK)