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Searched refs:QuadSPI_SR_AHB0NE_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h495 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
498 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h518 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
521 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h149 kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h912 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
915 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18816 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
18818 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19789 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
19791 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18348 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
18350 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18346 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
18348 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27647 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
27649 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27648 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
27650 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44341 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
44343 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46514 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
46516 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46514 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
46516 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46514 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
46516 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46514 #define QuadSPI_SR_AHB0NE_MASK (0x80U) macro
46516 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30649 #define QuadSPI_SR_AHB0NE_MASK 0x80u macro
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37848 #define QuadSPI_SR_AHB0NE_MASK 0x80u macro