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Searched refs:QuadSPI_SR_AHB0FUL_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h515 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
518 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h538 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
541 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h145 kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h932 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
935 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18828 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
18830 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19801 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
19803 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18360 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
18362 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18358 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
18360 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27663 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
27665 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27664 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
27666 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44357 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
44359 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46530 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
46532 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46530 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
46532 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46530 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
46532 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46530 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) macro
46532 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30657 #define QuadSPI_SR_AHB0FUL_MASK 0x800u macro
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37856 #define QuadSPI_SR_AHB0FUL_MASK 0x800u macro