Searched refs:QuadSPI_SMPR_HSENA_MASK (Results 1 – 7 of 7) sorted by relevance
18711 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro18717 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
19684 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro19690 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
18243 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro18249 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
18241 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro18247 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
27520 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro27526 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
27521 #define QuadSPI_SMPR_HSENA_MASK (0x1U) macro27527 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
30599 #define QuadSPI_SMPR_HSENA_MASK 0x1u macro
