| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/ |
| D | clock_config.c | 223 qspi->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK; in AT_QUICKACCESS_SECTION_CODE()
230 qspi->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); in AT_QUICKACCESS_SECTION_CODE()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/ |
| D | fsl_qspi.c | 352 base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); in QSPI_SoftwareReset()
366 base->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); in QSPI_SoftwareReset()
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_QUADSPI.h | 150 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
153 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_QUADSPI.h | 155 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
158 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HwAccess.h | 221 BaseAddr->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK; in Qspi_Ip_SwResetOn()
231 BaseAddr->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); in Qspi_Ip_SwResetOff()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/ |
| D | Qspi_Ip_HwAccess.h | 241 BaseAddr->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK; in Qspi_Ip_SwResetOn()
251 BaseAddr->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK); in Qspi_Ip_SwResetOff()
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 196 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
199 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/ |
| D | MK80F25615.h | 18317 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
18323 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 19290 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
19296 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/ |
| D | MK28FA15.h | 17821 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
17827 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/ |
| D | MK27FA15.h | 17819 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
17825 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 27272 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
27283 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 27273 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
27284 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 44052 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
44059 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46225 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
46232 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46225 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
46232 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 46225 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
46232 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 46225 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) macro
46232 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 30513 #define QuadSPI_MCR_SWRSTHD_MASK 0x2u macro
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 37710 #define QuadSPI_MCR_SWRSTHD_MASK 0x2u macro
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